用Verilog语言编写的实现NAND Flash块的控制存取以及同步的FIFO的控制

中频70M，30M带宽LFM信号，采样率为102.4M，，数字下变频后，还进行了三倍抽取，最后还得到I，Q两路信号 (IF 70M, 30M bandwidth LFM signal, the sampling rate 102.4M, under digital variable frequency after also carried out three times extracted, and finally also received the I and Q signals)

32位扰码器的verilog代码，编译通过(The Verilog code of 32_bit scrambler)

数字滤波器的C语言实现，，包含高通、低通、带通滤波器 (The C language implementation of the digital filter, including the high-pass, low pass, band-pass filter)

Generating a wider ALU from two small ones

ES A PRACRICA 2 DEL LABORATORIO DE DIGITAL

vhdl 让你更加熟悉掌握这么硬件电路设计语言 非常清晰(vhdl)

HDB3_verilog编码程序,附有文字解说,格式整齐,便于观看(HDB3_verilog coding procedures)

基于FPGA的频率相位可调DDS信号发生器-FPGA-based phase adjustable frequency DDS signal generator

本程序实现不同频率时钟的产生及其相互转化-this program different clock frequencies to the formation and transformation

VHDL语言实现的程序，功能如下：在键盘上输入什么，在相应的LCD上显示你输入的字符-VHDL language procedures, functions as follows: What is the keyboard input, in the corresponding LCD display the characters you type