讲解快速傅里叶变换

vhdl code for counterand detemines how counter works

verilog语言实现一个CPU，汇编程序实现汉明编码功能，输入11位代码，输出15位编码结果。(Verilog language to achieve a CPU, assembler to achieve Hamming coding function, enter 11 bit code, output 15 bit encoding results.)

说明：  fpga串口的发送程序基于verilog语言拿走不用谢。(The sending program of FPGA serial port is based on Verilog language.)

说明：  Matlab源程序，包括插值计算、积分微分等。(Matlab source code, including the interpolation calculations, differential and so on.)

说明：  VHDL BISS,SSI,ENDAT2.2, ENCODER

说明：  FPGA实现四位数与四位数乘法，有仿真波形，合理利用FPGA资源(Four-digit and four-digit multiplication is realized by using FPGA. It has simulation waveform and makes rational use of the resources of the FPGA.)

说明：  用verilog编辑的中值滤波器！语言旁表有注释方便理解！(Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!)

Matlab to hdl code for Least_square testbench

VERILOG HDL pid算法 带仿真验证(pid by verilog HDL)

周立功Verilog HDL黄金参考指南，学习VerriLog的东西。-Golden Week Ligong Verilog HDL reference guide, learning VerriLog things.