M25P80 serial memory for applications Verilog program

自己编写的只读存储器ROM16*8的试试很好用的-ROM 16*8

R S编 解 码 实 现 代 码 verilog语言(RS CODE AND ENCODE)

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.

verilog vga 图像处理(verilog vga)

FPGA AD数据采集模块，实现模拟信号到数字信号转换。(FPGA AD data acquisition module, the analog signal to digital signal conversion.)

基于EPM1270的PS2键盘鼠标驱动源码Verilog-Based on the EPM1270 the PS2 keyboard and mouse-driven Verilog source

说明：  PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller. Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website. The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in /opt/riscv32i[m][c]. See the build instructions below for details.

TI公司的DAC5578驱动程序，经测试过的，CSDN资源分享(DAC5578 Driver of TI Company Tested and CSDN Resource Sharing)

vhdl的源文件调试 ！！！！！！！！ flv视频-VHDL source file debugging! ! ! ! ! ! ! ! flv video