M25P80 serial memory for applications Verilog program

pcf8563，在quartusII下VERILOG编写的数字时钟程序，8位数码管显示(pcf8563, written in quartusII VERILOG digital clock program, eight digital display)

基于FPGA的希尔伯特变化的verilog代码(Hilbert change verilog code)

说明：  1、 例程功能VEYE-290-LVDS模组视频接入演示。（显示设备必须支持1080p/30或1080p/25的帧率） Veye模组—>MIA701开发板—>HDMI显示设备 2、 本例程硬件平台 MIA701-PCIE开发板，FPGA芯片：XC7A100TFGG484 3、 软件平台Vivado2018.1。 4、 附件含开发板原理图（底板+核心板）(1. Video access demonstration of routine function VEYE-290-LVDS module. (Display devices must support 1080p/30 or 1080p/25 frame rates) Veye Module - > MIA701 Development Board - > HDMI Display Equipment 2. The hardware platform of this routine MIA701-PCIE development board, FPGA chip: XC7A100TFG484 3. Software platform Vivado 2018.1. 4. Appendix contains schematic diagram of development board (bottom + core board))

FPGA中按键弹跳消除模块的研究与应用，原理和例子都非常好-FPGA to eliminate bounce in key research and application modules, principles and examples are very good

verilog实际例子，非常适合初学者学习(verilog practical examples, very suitable for beginners to learn)

THE SOURCE REALIZE THE TRANSFORMATION FROM YUV TO RGB

基于VHDL+FPGA的神经网络设计，实现简单的字符识别(Design of Neural Network Based on VHDL+FPGA to Realize Simple Character Recognition)

RAM存储器： 设定16 个8 位存储单元。如果read= 1 则dataout

SPH的原始代码，希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)

Implement the 7 segment diplay on spartan 3