M25P80 serial memory for applications Verilog program

说明：  点亮led流水灯，通过调用锁相环，可以更改对应的时钟。(Lighting the LED pipelining lamp, the corresponding clock can be changed by calling the phase-locked loop.)

Simple I2C controller -- 1) No multimaster -- 2) No slave mode -- 3) No fifo s -- -- notes: -- Every command is acknowledged. Do not set a new command before previous is acknowledged. -- Dout is available 1 clock cycle later as cmd_ack -Simple I2C controller-- 1) No multimaster-- 2) No slave mode-- 3) No fifo"s---- notes :-- Every command is acknowledged. Do not set a ne w command before previous is acknowledged.-- D is available out a clock cycle later as cmd_ack

HLD开发语言ADHL介绍。ADHL是ALTERA公司开发的硬件描述语言，也是一种较为流行的开发工具。是介绍AHDL的入门培训资料。-HLD development language ADHL introduction. ADHL is ALTERA developed hardware description language, but also a more popular development tools. AHDL is the introduction of induction training information.

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动检测(System Generator based image processing engineering, multimedia processing on FPGA source code, based on video motion detection)

吠陀乘数

说明：  DOCUMENT ON DISTRIBUTED ARITHMATIC

FPGA对SDRAM进行读写测试程序，亲测有效无误。(FPGA reads and writes test programs for SDRAM.)

华为内部资料，关于FPGA设计的详细过程介绍，很不错的。本文档从FPGA器件结构出发以速度路径延时大小和面积资源占用率为主题描述在FPGA设计过程中应当注意的问题和可以采用的设计技巧。(Huawei internal information, with regard to detailed FPGA design process of introduction, it is good. This document from the FPGA device structure in order to speed the path delay and area the size of the theme of the occupancy rate of resource description in the FPGA design process should pay attention to the problems and design techniques can be used.)

Implementation of Image Processing Algorithms in FPGA Hardware.

this project is about FIR FIlter By VHdl codes in the ISE.