M25P80 serial memory for applications Verilog program

ADI JESD204接口的ADC与Xilinx FPGA接口IP，包含Verilog和VHDL源代码，AXI总线接口，ADC串行控制接口(ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface )

说明：  是用VHDL语言编写的乐曲演奏程序，详细的写了各个模块的子程序(VHDL language is the music playing program)

数字秒表的VHDL设计,能精确到百分秒,在6位数码管上显示,分别有秒,分,小时,通过目标芯片EPF10KLC84-4验证-VHDL design of digital stopwatch, accurate to the percentage of seconds in the six digital tube display, respectively, have seconds, minutes, hours, through the target chips EPF10KLC84-4 verification

学习VHDL语言的范例，有关FSK-VHDL language learning paradigm, the FSK

基于CPLD的38译码器程序设计，使用VHDL语言编程，38译码器显示在数码管上。

GMSK调制基带眼图仿真源代码，基于MATLAB(GMSK modulation baseband eye diagram simulation source code, based on MATLAB)

timblogiw.c timberdale FPGA LogiWin Video In driver.

sdram 代码在最后要强调的是，本专题以技术为主，由于篇幅的原因，不可能从太浅的方面入手，所以仍需要有一定的技术基础作保证，而对内存感兴趣的读者则绝不容错过，这也许是您最好的纠正错误认识的机会！

VHDL servo control from technique of Pulse Width Modulation (PWM )

FFT implementation using C program