这是一个时钟的VHDL源代码，其中包含了源代码，以及工程。

用流水线的方法实现16位乘法器，运算速度快，消耗时钟资源少(Pipeline method to realize 16-bit multiplier, which is fast in operation and consumes less clock resources)

4 级流水方式的8 位全加器。。。。。。(Way flow of 4 full adder 8. . . . . .)

This is a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xilinx FPGA for adaptive equalizer and carrier recovery.

spartan-3e vhdl fpga 输入用滑动按钮代替 输出用led代替(spartan-3e VHDL fpga input with sliding button instead of the output with led instead)

代码风格非常好，容易看懂，移植性高

DAC0832 接口电路程序.功能：产生频率为762.9Hz的锯齿波DAC0832VHDL程序与仿真-DAC0832 procedures interface circuit. Functions: generate the sawtooth frequency of 762.9Hz and simulation procedures DAC0832VHDL

基于Verilog的小波滤波器程序设计的总结文档。(Verilog based wavelet filter program design summary document.)

实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)

8通道同步AD芯片7608的FPGA控制程序(FPGA control program of ad7608(8 channel synchronous AD chip))

Toplevel VHDL Structural model of a system containing 8051 -Toplevel VHDL Structural model of a system containing 8051