ep2c5 实现 逻辑门 verilog语言，quartus 2 仿真

一位加法全加器，可以实现低位进位输入和高位进位输出。(full adder)

自动化仿真平台的搭建使用代码，经过具体的仿真和优化，发现代码完全可用(The automated simulation platform is built using code, and after specific simulation and optimization, it is found that the code is fully available)

说明：  fPGA中的竞争冒险现象的来源及其解决方法(FPGA in the source of the phenomenon of competitive risk-taking and their solutions)

System Verilog decodificator. Enters a value(binary), drops hundreds, tens and units in BCD

uart documentation, july 17, 2019. the document describes the basics of verilog programming and how to implement them on an fpga device

这时一个数字钟的VHDL程序，有计时、校时、整点报时功能，很适合做EDA设计之用-When a digital clock in VHDL procedures, time, school hours, the whole point timekeeping function, it is suitable for use in EDA Design

本人初学VHDL时编的比较系统的VHDL源程序 巨实用 (I am learning more systematic series of practical VHDL source Giant)

说明：  激光测速研究，主要介绍多普勒激光测速知识(Laser velocimetry study introduces laser-Doppler velocimetry knowledge)

实现一个简单的电子钟，其时间（时，分，秒）可以设置和更改，设置和更改的同时不会影响其他显示的变化（相互独立）。-achieve a simple electronic bell, the time (hours, minutes and seconds) can set and change, Settings and change will not affect the other shows the change (independent).

实现二项混合式步进电机的驱动，和步进电机的细分程序。(The driving of binomial hybrid stepper motor and the subdivision program of stepper motor are realized.)