fpga DDS ROM数据正弦波形正半周采样程序

基于Verilog的FPGA设计时序分析约束详细解释与使用方法(FPGA timing constraints)

8051MCU在FPGA上实现的源代码，用VHDL语言编写-8051MCU in the FPGA to achieve the source code, using VHDL language

基于FPGA的图像采集卡的设计与相关说明-FPGA-based design of frame grabbers and related note

DDR2 SDRAM 控制器的FPGA实现-DDR2 SDRAM controller FPGA to achieve

使用verilog写的32位浮点数加法模块、浮点数乘法模块、浮点数除法模块、浮点数指数模块。指数模块是综合前面三个例化成泰勒级数求指数，迭代次数（可设置）决定了精度。(Use verilog write 32-bit floating-point addition module, floating-point multiplication module, floating-point division module, the floating point number index module.Index module is a comprehensive index of the front three cases into Taylor series for calculating index, the number of iterations can be set to determine the precision)

实用的程序代码，希望对大家有用，已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through

HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License

本程序调试了TI的高精度模数转换芯片ADS1115,此模数转换器采用双积分型，16位，为IIC通信方式，调试较复杂，在对直流采集方面有着广泛的应用(This program debugging TI s high-precision analog-digital conversion chip ADS1115)

说明：  采用vhdl语言编写的卷积编码（2.1.7），通过调试可直接下载使用(Convolution using vhdl language code (2.1.7) can be directly downloaded through the use of debugging)

nrf24l01发送代码，verilog实现NRF24L01通信(NRF24L01 send code, Verilog to achieve NRF24L01 communication)