FPGA

由VHDL 语言实现的数控分频 利用的是QUARTUES环境已经得到验证-By the NC VHDL language is the use of sub-frequency QUARTUES environment has been tested

基于TCAM的高速路由查找，逻辑实现深度为32的内容查找，得到索引和命中指示(TCAM lookup based on a high-speed routing logic to realize the depth of content to find 32, get indexed and hit instructions)

PCI Arbitor by VHDL -PCI Arbitor by VHDL

100个VHDL的例子-100 examples of VHDL

HARIS角点检测Harris角点检测HARRIS CORENR探测器

VHDL的动态扫描显示六个数码管，包含分频代码产生25kHz的扫描信号作为时钟。(VHDL dynamic scanning display six digital tube contains 25kHz scanning signal is generated as a clock divider code.)

实施256点，

Verilog数字系统设计教程【夏宇闻】原书第十章：IIC总线接口模块设计代码包-verilog program for iic bus design. the pakege includes iic protocl master program and behavel slavle program, even includes testbench and data bat files.

一个vhdl实现的hamming码编码器-an hamming coder using vhdl

主要通过频率分配 实现不同时间的变化 达到呼吸一闪一闪的效果