自己今年的毕业设计DDS波形发生器,有正弦波,方波,三角波,锯齿波....

基于verilog语言的数据选择器，包括数据选择器的测试模块 (verilog language based on the data selector, including data selection for the test module)

这个文件中是UltraEdit的一些格式化文件说明 由于原来的 UltraEdit 不支持 HDL 语言的格式化显示，把文件解压得到的 wordfile.txt替换其安装目录下的 wordfile.txt 文件即可-This document is formatted UltraEdit document describes some of the original UltraEdit as a result of HDL does not support formatting language shows that the document received decompression wordfile.txt replace its installation directory under the document can wordfile.txt

网卡的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me.-NIC

verilog da0832 cpldfpga control-verilog da0832 cpldfpga control

(2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through

采用VHDL硬件描述语言实现的双口径RAM块存储器的初始化(VHDL hardware description language using the dual-caliber RAM block memory initialization)

vhdl波形发生程序.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 各种波形的线形叠加输出。 -vhdl waveform occurred procedures. 4 achieve common sinusoidal waveform, 1.30, sawtooth, square-wave (A, B) the frequency and amplitude control output (square A duty cycle is also controllable), can store data of arbitrary waveform characteristics and able to reproduce the waveform, but also through a variety of linear superposition of the waveform output.

verilog实现mp3解码程序，包括testbench(mp3 decoder verilog implementation procedures, including the testbench)

fpga verilog实现 S29GL256S 系列 并行 nor flash 的读写擦除操作功能。 verilog源代码。(Verilog S29GL256S to achieve FPGA series parallel flash nor read and write erase operation function. Verilog source code)

手机号码归属地查询,代码详尽，简单易懂，欢迎使用！-hello!welcome to my code !thank you !