全部通过，是我的精心设计，完全满足初学者的要求。

通信系统中数据的传输以帧为单位，在FPGA中帧头检测是通信系统中的一部分，该程序实现了FPGA中帧头的检测。(Transmission of data in a communication system in units of frames, the frame header is detected in the FPGA part of the communication system, the realization of the frame header is detected in the FPGA.)

FPGA，VHDL语言 ：分频1S 8位流水灯，适用于所有FPGA芯片，VHDL源程序！！(FPGA, VHDL language: divide-1S 8 light water, and apply to all FPGA chip, VHDL source code! !)

设计了一个电子时钟，功能包括定点报时，设置闹钟，校时等(Designed an electronic clock, features include fixed-point timekeeping, setting alarms, school hours, etc.)

xilinx公司的FPGA实现数字视频信号处理器。语言是VHDL。-Xilinx FPGA to achieve the company

vhdl学习方法,含有大量的vhdl源代码,对vhdl的语法的介绍-VHDL source习laugh Yang, Yi bleed at the nose cavity submerged stresses measured tungsten Daitou VHDL, VHDL-Qin Pang Yang cavity cavity Geng Zhuang

最终FFT 64点使用定点。

this Code is in verilog HDL. This Code is for piplined processor with 4 opcode. this will work in three cycle latch, decode and exicute.. test bench for xilinx ise is laos given

非常有用的IP核资源，里面包含了JTAG,MEMORY,PCI，SDRAM和USB1.1等内容，期望对大家有用-A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, and USB1.1 and other content, expectations for all of us

一个数码管的驱动开发程序，程序完备，可以直接使用，在开发板上使用时注意改变引脚(A digital control of the driver development program, the program is complete, can be used directly, when used in the development of attention to change the pin board)

基于FPGA编写的verilog代码，在xilinx上仿真实现FFT变换(FPGA-based verilog code written in xilinx FFT transform Simulation)