带同步复位信号的二分频VHDL 程序

report for a report for a class

基于verilog的DDS设计,内附代码,仿真环境等说明(the DDS design based on verilog)

de2 vga控制器，也可用于其他板子开发-de2 vga controller board can also be used for other development

FPGA控制AD7321的模块，是本人亲自试验过的。有Verilog源码，和简单文档(Fpga control module of ad 7321, is I personally tested. Verilog source code, and simple documentation)

this is an peak detection alguritm,in this matlab code u can clean base line noise to have clear ECG signal

基于FPGA的DDS相位累加器，连接至存有波形数据的rom后再接至DA可以输出对应的波形(abcdefghijklmnopqrstuvwxyz)

基于FPGA的32阶FIR数字滤波器设计 源程序。设计使用了并行乘法器，运行速度更快，占用内存更小，延迟更小。 (32 order FIR digital filter based on FPGA design source program. Design USES parallel multiplier, faster and less memory, less delay.)

已经正式出版，西安电子科技大学出版社，FPGA设计及应用，作者褚振勇(Has been officially published, Xi' an University of Electronic Science and Technology Publishing House, FPGA design and application, the author Zhezhengyong)

把指定的噪声叠加到信号上去.有标准噪声库NOISEX-92，其中带有白噪声、办公室噪声、工厂噪声、汽车噪声、坦克噪声等等，在信号处理中往往需要把库中的噪声叠加到信号中去，而噪声的采样频率与纯信号的采样频率往往不一致，需要采样频率的校准。 (The specified noise superimposed to the signal up. Standard noise library NOISEX-92, with white noise, office noise, factory noise, car noise, tank noise in the signal processing often requires noise to be superimposed in the library The signal to noise of the sampling frequency and pure signal sampling frequency is often inconsistent sampling frequency of calibration.)

pcf8563，在quartusII下VERILOG编写的数字时钟程序，8位数码管显示(pcf8563, written in quartusII VERILOG digital clock program, eight digital display)