16*16点阵显示”北京欢迎"

使用verilog语言进行编码 完成mdio接口访问phy8201芯片的功能(Use verilog language to encode the mdio interface to access the function of phy8201 chip)

数字钟通过verilog实现，并且支持Modelsim仿真，通过实验验证(The digital clock is implemented by Verilog and supports Modelsim simulation)

以太网的FPGA程序实现以太网的FPGA程序实现以太网的FPGA程序实现(enternet verilog fpga)

说明：  This is code of UVM CALLBACK function.

说明：  用于FPGA设计的代码（Verilog代码），在FPGA设计中的高速串并转换，时钟提取，对齐处理等功能(for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on)

Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.

Xilinx Sysgen User Guide

FPGA实现FFT算法的源代码及工程文件，此工程为ISE工程项目。有详细的说明，可以运行。(FPGA Implementation of FFT algorithm source code and project files, this works for the ISE project. There are detailed instructions, you can run.)

用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS-(use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-)

一个具有置位、复位、左移和右移功能的八位移位寄存器/“01011010”序列检测器。移位寄存器电路端口为：异步清零输入端口rst，输入时钟clk，置数判断输入端口load，移位类型判断输入端口m，数据输入端口data[7:0]，输出端口q[7:0]。序列检测器电路端口为：异步清零输入端口rst，输入时钟clk，串行数据输入端口d，输出标志端口s。(A eight bit shift register / 01011010 sequence detector with set, reset, left shift, and right shift function. Shift register circuit port is: Asynchronous Clear input port rst, input clock CLK, set the number to determine the input port load, shift type to determine the input port m, data input port data[7:0], output port q[7:0]. The sequence detector circuit port is: Asynchronous Clear input port rst, input clock CLK, serial data input port D, output flag port s.)