16*16点阵显示”北京欢迎"

说明：  本设计是基于FPGA的高速并行接口通信接口和协议设计，该设计使用的是8 位并行接口，通过配置FPGA的FIFO寄存器保证了在高速并行下的数据稳定性，在 最终的测试中，该协议能够稳定传输的速度为80Mbps。(This design is based on FPGA high-speed parallel interface communication interface and protocol design, the design uses 8 Bit parallel interface ensures the data stability under high-speed parallel by configuring the FIFO register of FPGA. In the final test, the protocol can stably transmit at 80 Mbps.)

说明：  USB主机和设备的verilog代码，实现了USB1.1协议规范的要求(USB host and equipment Verilog code to achieve the USB 1.1 protocol specification requirements)

this a LCD Driver VHDL code -this is a LCD Driver VHDL code

高速流水的SDRAM控制器，最高速度可达速度在200M左右(high speed SDRAM controller)

simple code of some kind of base decoder based on verilog

Altera官网上关于SOPC中自定义组件（PWM）的实例，官网上现在没了。。可很多书上都在用-Altera in the official line on the SOPC custom component (PWM) of the examples are not the official line. . Can be a lot of books are in use. . .

Lift Controller in vhdl using process statement and state disgram

锡林克斯巴达官方文件有详细说明，支持斯巴达、顶点

说明：  该模块实现了FPGA的uart串口收发功能(The module realizes UART serial port transceiver function of FPGA)

说明：  QPSK 调制 与 解调的源代码 可综合 出波形(QPSK modulation and demodulation of the source code)