一个I2C从机代码

verilog 实现的FFT 流水线操作，速度能达到200M(verilog pipelining the FFT implementation, the speed can reach 200M)

说明：  用verilog编写的ddr3芯片读写控制程序，经过调试的，可以直接拷贝。已在Xilinx Spartan6 FPGA调试验证。(The ddr3 chip read-write control program written in verilog can be copied directly after debugging. Tested and verified on Xilinx Spartan6 FPGA.)

基于SHA-1算法和DS28E01加密芯片的FPGA系统设计，该上传文件为整个设计的系统文件。Quarter软件编程的Verilog程序，包含仿真调试界面。(Design of FPGA system based on SHA-1 algorithm and DS28E01 encryption chip。)

Xilinx ISE 9.2 and ChinpScope Pro 9.2 Sn

offset_cancellation code for matlab to hdl

un controller pi par le langage VHDL xilinx ise design 13.2

LATTICE FPGA FIFO 程序例程，工程详细，全部源代码上传 (LATTICE FPGA FIFO routine, detailed engineering, all source code uploaded)

基于verilog语言的差分曼彻斯特编码，内包含数据的采集，CRC校验（8位），和编码，输出。附有完整的工程文件。可直接调用modelsim仿真。(Based on differential Manchester encoding verilog language, and contains data collection, CRC check (8), and coding. With complete project file. Modelsim simulation can be called directly.)

PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt controller. Tools (gcc, binutils, etc..) can be obtained via the RISC-V Website. The examples bundled with PicoRV32 expect various RV32 toolchains to be installed in /opt/riscv32i[m][c]. See the build instructions below for details.

美光MT25Q系列NOR Flash测试模型(Micron MT25Q Series NOR Flash Test Model)