Verilog模块的缓存设计

基于fpga的位同步信号提取仿真 使用vhdl语言 quartus(To use vhdl language quartus fpga bit synchronization signal extraction-based simulation)

直接序列扩频系统的收发系统，可以进行参数配置(this is a Verilog program )

RS(255,223)编解码算法。verilogHDL代码实现，在XILINX的芯片上得到验证。不包含任何IP核，方便移植到任何FPGA芯片。(RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.)

OFDM_TX_CR802.11-master 802.11协议 ofdm开发(OFDM_TX_CR802.11-master)

利用verilog编码，设计运动员反应测试时间的电路，共有三个输入，枪声、运动员和复位信号，另外，认为反应时间不可能小于200ms，因此当测量时间小于200ms时 会发出警报

说明：  基于数码管独立显示和三色灯的交通指示系统设计(Design of Traffic Indicator System Based on Digital Tube Independent Display and Tri-color Lamp)

Encryption has become a part and parcel of our lives and we have accepted the fact that data is going to encrypted and decrypted at various stages. However, there is not a single encryption algorithm followed everywhere. There are a number of algorithms existing, and I feel there is a need to understand how they work. So this text explains a number of popular encryption algorithms and makes you look at them as mathematical formulas.

这是基于Quartus2 开发环境和verilog hdl语言写的38译码器(This is based development environment and Quartus2 verilog hdl language used to write decoder 38)

利用matlab提供的firhalfban函数设计阶数为16、通阻带容限为0.0001的半带滤波器。仿真测试滤波前后的信号时域图，回执滤波器的频率响应特性图(Provided firhalfban function using matlab design order of 16, through the 0.0001 stopband wool half-band filter. Simulation test filtered time domain signal before and after, receipt filter frequency response characteristic diagram)

it is a fir filter program VerilogHDL.(it is a filter program VerilogHDL fir.)