Verilog模块的缓存设计

完成GPS的IRIG_B码解码，已经模块化，并且有详细的中文注释(Completed the GPS IRIG_B of decoding modular, and there are detailed notes in Chinese)

ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER

基于QuartusII环境下的地铁自动售票系统(Subway auto ticketing system based on QuartusII)

这里是verilog代码 ；8bit  ；吠陀乘数还可以使用这个模块的设计…你想要更大的…

开源的ULPI IP核，可用于USB3300芯片的开发(openSource ULPI IP core which could be used for USB3300 chip development)

VHDL Code For Full Adder By Data Flow Modelling

说明：  FPGA控制AD7656和模拟开关实现36路模拟量循环采集(FPGA control AD7656 and analog switch to realize 36 channels of analog cyclic acquisition)

RS422通信程序，Verilog语言，此模块实现422通信功能(RS422 communication program, Verilog language, this module implements 422 communication function.)

文件名：lcd1602lib.h 内　容：1602液晶的控制端口、数据端口和相关操作(The file name: lcd1602lib. H * inside let: 1602 LCD control port, data port and related operations )

针对电力电子领域的需求，采用自然采样法设计了一个全数字三相SPWM信号产生系统IP软核．通过数字频率合成技术实现了对电源频率的辅确控制．使电源频率精度达到16位．其中。通过调节控制参数．分别实现了电源频率与载波频率的7级、8级控制．最后。搭建了基于FPGA的测试系统．验证了系统功能的正确性．(According to the requirement of power electronics, the natural sampling method for the design of a full digital three-phase SPWM signal generation system. The power frequency of IP core is the auxiliary control is implemented through digital frequency synthesis technology. The power frequency accuracy of 16. By adjusting the control parameters, 7 and 8 levels of power frequency and carrier frequency are realized respectively. Finally, the control of the power frequency and carrier frequency is realized. A test system based on FPGA is built, which verifies the correctness of the system function)