fifo

使用Verilog编写的时间同步模块，解决位同步问题，ISE12.2下编译通过(Time synchronization module written in Verilog, bit synchronization issues under ISE12.2 compiled by)

用verilog实现ldpc最小和译码算法(This code is for the decode of MS-algorithm based on LDPC.)

《精彩51单片机教程》适合初学者，很难得(" Discover the 51 SCM Guide" for beginners, very rare)

spartan-3e fpga vhdl 实现的计数器 记满后点亮小灯(spartan-3e fpga vhdl counter to light led)

说明：  basic verilog code on siso, piso, sipo

用vhdl写实用96例子, 有RAM，PID 等(Using VHDL to write practical examples of 96, there are RAM, PID and so on)

广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)

FPGA实现四位数与四位数乘法，有仿真波形，合理利用FPGA资源(Four-digit and four-digit multiplication is realized by using FPGA. It has simulation waveform and makes rational use of the resources of the FPGA.)

基于FPGA的数字低通滤波器 。。。。。(FPGA-based digital low-pass filter。。。。。)

74ls138组成16..4线编码器 经过本人验证(74ls138 composed of 16 .. 4 line encoder after I verify)