AXI VDMA 数据表

基于有限状态机的咖啡自动售货机。 自动售货机应出售茶为 Rs。 10、 咖啡为 Rs。 20 和冷咖啡为 Rs.30。 这台机器接受 Rs。 10 和 Rs.20 注意到。 如果选择的产品超出支付的金额，金额返回和显示一条消息。

描述了IC-hus公司推出的BISS-C协议内容，包括单向biss-c协议以及标准biss-c协议(Describes the BISS-C protocol introduced by IC-hus, including the one-way biss-c protocol and the standard biss-c protocol)

HDB3码在matlab中的仿真，包括原始码、AMI码及HDB码的相关仿真图形(HDB simulink in matlab)

用VERILOG实现一个被除数为8位、除数为4位的高效除法器(With VERILOG implement a dividend for the 8-bit, 4-bit effective divisor divider)

说明：  LTE is an abbreviation for Long Term Evolution.

Due to its high modularity and carry-free addition, a redundant binary (RB) representation can be used when designing high performance multipliers. The conventional RB multiplier requires an additional RB partial product (RBPP) row, because an error-correcting word (ECW) is generated by both the radix-4 Modified Booth encoding (MBE) and the RB encoding. This incurs in an additional RBPP accumulation stage for the MBE multiplier. In this paper, a new RB modified partial product generator (RBMPPG) is proposed; it removes the extra ECW and hence, it saves one RBPP accumulation stage.

单周期16位CPU的设计,我们的计算机组成原理课设，可以实现R型、I型和J型指令，内有报告和指导书(Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions)

这是Verilog的加法器的代码。并且还包括：脉动进位加法器。我希望这将是对你有帮助。

这是一个FIFO_Buffer的verilog代码.(This is a FIFO_Buffer the Verilog code.)

基于Xilinx Spartan6的 一个简单的CPU MU0 VHDL(Based on a simple CPU Xilinx Spartan6 of MU0 VHDL)