AXI VDMA 数据表

说明：  ucos II 中文手册额，可以学习一下哦(UCOS II Chinese manual volume, you can learn it)

zybo-Embedded System Design Flow on Zynq 实现ZYBO接受串口的数据，然后将键盘数据的4位二进制码通过四个LED灯显示：

verilog语言实现的cordic算法，计算sin cos三角函数

异步fifo，实现的方法是MSB，满足慢时钟域到跨时钟域的数据传输，也满足快时钟域到慢时钟域的数据传输。

FPGA Implementation ofLow Power 64-Point Radix-4 FFT Processor for OFDM System

该例子是基于sopc的IIC总线设计完整设计，分为硬件和软件部分，软件部分是用c语言编写的。该项目是个以完成的项目，据有较高的参考和经济价值。该例子是原来做过的项目。 整个项目是在Quartus II 7.0和nios IDE环境下开发。 (This example is based on the IIC bus design sopc complete design, divided into hardware and software, the software part is written in c language. The project is to complete the project, according to the reference and a higher economic value. The example is a project originally done. The whole project is in the Quartus II 7.0 and the nios IDE development environment.)

verilog语言写的一个四层电梯程序，有优先级的判断。(verilog language of a four-story elevator procedures to determine priority.)

led学习控制l44444444444444(led verilog led ccccccc)

基于FPGA的16QAM调制程序,基于verilog开发环境(16QAM modulation program based on FPGA-based development environment verilog)

《Altera FPGA_CPLD设计 高级篇》详细介绍FPGA应用于高级特性，LogicLock设计，时序约束，设计优化，高级工具及系统级设计技术，是深入学习FPGA的重要材料(" Altera FPGA_CPLD advanced part design" details FPGA used in advanced features, LogicLock design, timing constraints, design optimization, system-level design tools and advanced technology, in-depth study is an important material for FPGA)