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咖啡自动售货机 verilog 代码与验证平台
基于有限状态机的咖啡自动售货机。
自动售货机应出售茶为 Rs。 10、 咖啡为 Rs。 20 和冷咖啡为 Rs.30。
这台机器接受 Rs。 10 和 Rs.20 注意到。
如果选择的产品超出支付的金额,金额返回和显示一条消息。
- 2022-01-26 00:14:51下载
- 积分:1
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BISS-c协议中英文版本
描述了IC-hus公司推出的BISS-C协议内容,包括单向biss-c协议以及标准biss-c协议(Describes the BISS-C protocol introduced by IC-hus, including the one-way biss-c protocol and the standard biss-c protocol)
- 2021-05-10 10:18:53下载
- 积分:1
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HDB3
HDB3码在matlab中的仿真,包括原始码、AMI码及HDB码的相关仿真图形(HDB simulink in matlab)
- 2020-07-04 19:40:02下载
- 积分:1
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divider
用VERILOG实现一个被除数为8位、除数为4位的高效除法器(With VERILOG implement a dividend for the 8-bit, 4-bit effective divisor divider)
- 2020-11-19 11:39:37下载
- 积分:1
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C-V2X-master
说明: LTE is an abbreviation for Long Term Evolution.
- 2019-06-29 01:08:09下载
- 积分:1
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code
Due to its high modularity and carry-free addition, a redundant
binary (RB) representation can be used when designing high performance
multipliers. The conventional RB multiplier requires an additional RB partial
product (RBPP) row, because an error-correcting word (ECW) is generated
by both the radix-4 Modified Booth encoding (MBE) and the RB encoding.
This incurs in an additional RBPP accumulation stage for the MBE multiplier.
In this paper, a new RB modified partial product generator (RBMPPG) is
proposed; it removes the extra ECW and hence, it saves one RBPP
accumulation stage.
- 2017-10-01 23:34:56下载
- 积分:1
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16-bit-CPU
单周期16位CPU的设计,我们的计算机组成原理课设,可以实现R型、I型和J型指令,内有报告和指导书(Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions)
- 2020-08-02 10:28:35下载
- 积分:1
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Verilog 加法器代码
这是Verilog的加法器的代码。并且还包括:脉动进位加法器。我希望这将是对你有帮助。
- 2022-12-23 13:25:03下载
- 积分:1
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FIFO_Buffer(verilog)
这是一个FIFO_Buffer的verilog代码.(This is a FIFO_Buffer the Verilog code.)
- 2021-04-22 13:38:49下载
- 积分:1
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mu0
基于Xilinx Spartan6的
一个简单的CPU MU0
VHDL(Based on a simple CPU Xilinx Spartan6 of MU0 VHDL)
- 2020-12-07 08:29:22下载
- 积分:1