同步FIFO verilog

verilog source code for SD card SLAVE DEVICE IP-Core

从bt656数据流中提取出同步信号, 适合于搞fpga/cpld开发调式(bt656 internel sync to extern sync singal， bt656 internel sync to extern sync singal)

本代码包适用于DE1-SOC开发板，本代码包适用于南昌大学2019EDA实验，使用Verilog HDL编写，代码包括六个实验：四位全加器、模可变计数器、序列检测器、交通灯、计数器、DDS。

verylog语言编程，为异步flipflop的程序。具有数据传输功能，数据位数可以用户设定(verylog language programming for asynchronous Flipflop procedures. With a data transmission function, data can be user set the median)

说明：  对温湿度采集芯片进行配置并且把读到的温度数据显示到数码管上(The temperature and humidity acquisition chip is configured and the temperature data read is displayed on the nixie tube)

xilinx ise开发环境中fft IP核调用，仿真(Xilinx ise development environment FFT IP core call, simulation)

内容有VHDL语法总结及相应的实例应用，每个程序我都亲自试过，特别适合初学VHDL的同学们。常用的程序有 设计一个M序列发生器，M序列为“11110101”、 设计一个彩灯控制器，彩灯共有16个，每次顺序点亮相邻的四个彩灯，如此循环执行，循环的方向可以控制。设计一个跑马灯控制器。一共有8个彩灯，编号为LED0~LED7，点亮方式为：先从左往右顺序点亮，然后从右往左，如此循环往复等等。这些都是我在考试前熬夜总结的，很有用。如果配合开发板用的话，那就更好了 ( VHDL syntax summary content and the appropriate application instance, every program I have personally tried, especially for students of beginner VHDL. Common program has designed a sequence generator M, the M series is 11110101 , a lantern controller design, a total of 16 lights, each sequence of four adjacent lights lit, so the cycle execution cycle direction can be controlled. Marquee design a controller. A total of eight lights, numbered LED0 ~ LED7, the lighting way: first left to right order of light, and then right to left, so the cycle and so on. These are all I stay up all night before the exam summary, very useful. When combined with the development board, then so much the better )

阿尔法贝塔滤波器，是卡曼滤波器的简化，比卡曼滤波器速度快。这是一个实例。(aplha-beta filter is filter that faster than kalman filter)

说明：  access must be conf urr arr

虽然Loeffler DCT实现了良好的质量转换