同步FIFO verilog

说明：  altera 最新的CYCLONE IV的pci-e核的testbench，VHDL源程序。(altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.)

verilog语言写的一个四层电梯程序，有优先级的判断。(verilog language of a four-story elevator procedures to determine priority.)

基于FPGA用verilog语言实现16点FFT(16-point FFT FPGA-based verilog language)

polyphase fir dilter

Convert Roman numerals to integers

在FPGA平台实现SPI传输协议开发，SPI为三总线式。(Implementation of SPI transmission protocol development on FPGA platform)

针对某船舶模型定位系统中调速电机，以FPGA(现场可编程门阵列)为控制器，采用数字比例积分调节器实现电机的速度控制算法，设计出数字化调速控制器(Positioning system for a ship model in the motor speed, the FPGA (field programmable gate array) for the controllers, proportional integral regulator with digital speed of the motor control algorithm, designed digital speed controller)

录像带上 ALtera DE2 教育委员会，旋风 2 EP2C35F672C6

DAC0832 接口电路程序.功能：产生频率为762.9Hz的锯齿波DAC0832VHDL程序与仿真(DAC0832 procedures interface circuit. Functions: generate the sawtooth frequency of 762.9Hz and simulation procedures DAC0832VHDL)

液晶显示屏显示汉字“年”的驱动程序VHDL(nian VHDL)