Verilog Jpeg 编码器

ad7705通过spi时序进行读写，通过fpga模拟spi时序对adc进行读写，首先写入通信寄存器20h，时钟寄存器0C，通信寄存器10，设置寄存器40H，然后写通信寄存器进行读取。

使用FPGA做的数码相册实验，用NIOS做了FAT32文件系统和JPEG图像解码,FPGA和SDRAM做了显示的缓存(Using FPGA to do the digital album experiment, using NIOS to do the FAT32 file system and JPEG image decoding, FPGA and SDRAM to do the display cache)

A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.

设计一个哈夫曼编码器 要求对一段数据序列进行哈夫曼编码，使得平均码长最短，输出各元素编码和编码后的数据序列。 ① 组成序列的元素是[0-9]这10个数字，每个数字其对应的4位二进制数表示。比如5对应0101，9对应1001。 ② 输入数据序列的长度为256。 ③ 先输出每个元素的编码，然后输出数据序列对应的哈夫曼编码序列。(Designing a Huffman Encoder Huffman coding is required for a data sequence to minimize the average code length and output the coded and coded data sequence of each element. (1) The elements that make up the sequence are the 10 digits [0-9], and each digit is represented by its corresponding 4-bit binary number. For example, 5 corresponds to 0101, 9 corresponds to 1001. (2) The length of the input data sequence is 256. (3) First output the encoding of each element, and then output the Huffman encoding sequence corresponding to the data sequence.)

图像采集、存储控制verilog源代码(Image acquisition, storage, control of Verilog source code)

VHDL汇编语言原理及源代码。spartan 3e开发板试用。(VHDL language.)

Complex of three-point Gauss-lengend the Formula pi, Including orbital maneuvering simulation, initial orbit calculation, University of numerical analysis algorithms.

16位有符号和无符号乘法器FPGA源代码(16-bit signed and unsigned multiplier FPGA source code)

用zynq实现片内的数模转换，基于最新的zynq平台(zynq xadc on FPGA arm)

it is a new describng system for it field