用vhdl实现脉冲宽度可控的一简单程序 仿真环境MAXPLUS

开源软核处理器OpenRisc的SOPC设计

vhdl um teste com muita coisa interessante ae pra ver

CPLD LATTICE1032测试模式代码-CPLD LATTICE1032 test model code

基于FPGA的希尔伯特变化的verilog代码(Hilbert change verilog code)

application of a galois field multiplication and normal multiplication

DSP 程序的测试 很有用的 仪器上面用的-DSP testing procedures very useful in the above apparatus

说明：  基于FPGA的Veilog HDL实现代码，简单明了，希望能帮助verilog的初学者……(ＤＤＳ　based on Verilog ＤＨＬ for FPGA　)

通信系统中的基带信号处理中的成型滤波器代码，已经通过编译。(Communication system baseband signal processing shaping filter code, has passed the compilation.)

详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE(Detailed description of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE)

E1 deframmer and Frammer.