wishbone 源代码，opencore

1、用状态机设计A/D转换器ADC0809的采样控制电路，并在数码管上显示转换结果； 2、设置有复位和启动/保持开关，要求 ⑴ 复位开关用来使A/D转换器复位，并做好A/D转换准备； ⑵ 启动/保持开关用来控制A/D转换器开始连续转换或停止转换保持结果，即按一下启动/保持开关，启动A/D转换器开始转换，再按一下启/停开关，停止转换并保持结果。 3、采用Verilog HDL语言设计符合上述功能要求的控制电路。(1, with the state machine design A/D converter ADC0809 sampling control circuit and display the results on the digital conversion 2 is provided with a reset and start/hold switch, reset switch is used to make the request ⑴ A/D converter reset and do A/D conversion ready ⑵ start/hold switch is used to control the A/D converter starts converting or stop the conversion to maintain a continuous result that by clicking Start/hold switch, start the A/D converter to start the conversion, and then Click the start/stop switch stops the conversion and keep the results. 3, using Verilog HDL language designed to meet the functional requirements of the above-mentioned control circuit.)

ALTERA发布的内部FIFO读写示例，很有参考价值，对初学者会有一定的帮助(ALTERA' s internal FIFO read and write examples of great reference value, there will be some help for beginners)

此为数学形态滤波器消燥的代码，用于一维信号，涉及一个具体的例子，需要的话可以自己修改，修改相应的结构元素。(This is a mathematical morphology filter away dry code, used to one dimensional signal, involving a concrete example, necessary can change ourselves, change the structure of the corresponding elements)

说明：  1、 例程功能VEYE-290-LVDS模组视频接入演示。（显示设备必须支持1080p/30或1080p/25的帧率） Veye模组—>MIA701开发板—>HDMI显示设备 2、 本例程硬件平台 MIA701-PCIE开发板，FPGA芯片：XC7A100TFGG484 3、 软件平台Vivado2018.1。 4、 附件含开发板原理图（底板+核心板）(1. Video access demonstration of routine function VEYE-290-LVDS module. (Display devices must support 1080p/30 or 1080p/25 frame rates) Veye Module - > MIA701 Development Board - > HDMI Display Equipment 2. The hardware platform of this routine MIA701-PCIE development board, FPGA chip: XC7A100TFG484 3. Software platform Vivado 2018.1. 4. Appendix contains schematic diagram of development board (bottom + core board))

altera详细使用配置手册，有一定的参考价值，写的比较详细-altera in detail the use of manual configuration, has a certain reference value, a more detailed written

1024点快速傅里叶变换，使用verilog hdl硬件描述语言(1024point FFT，using verilog hdl)

基于ALtera公司的若干款FPGA的调试经验，对初学者有重要价值-ALtera a number of sections based on the company" s FPGA debugging experience, great value for beginners

Convolutional neural network code for fpga

说明：  DAC3283 寄存器初始化，SPI驱动(Dac3283 register initialization, SPI drive)

Construction and Experimental Evaluations of User-Centered Power