master and slave code

vhdl的很多例子，包括LED、lcd、按键、数码管等等，非常的实用。-VHDL of many examples, including the LED, lcd, keypad, digital control and so on, very practical.

本程序实现流水线功能，您可根据自己需要更改参数，试用芯片xilinx，用verilog语言编写(This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language)

一个简单的UCOSII操作系统，在DE2上面调试通过(A simple UCOSII operating systems, debugging through the DE2 above)

CSC RGB2YUV Verilog source code

卷积码（2,1,4）编解码的FPGA实现(Convolution code (2,1,4) decoding the FPGA implementation)

说明：  FPGA实现Jpeg压缩，和视频采集程序(Zynq - Main - register access Mio)

LDPC encoder and decoder, very simple

基于avgt开发板的jesd204b源代码，需要安装Quartus软件(Avgt development board based on the jesd204b source code)

FPGA实现四位数与四位数乘法，有仿真波形，合理利用FPGA资源(Four-digit and four-digit multiplication is realized by using FPGA. It has simulation waveform and makes rational use of the resources of the FPGA.)

同步FIFO功能，verilog语言描述，通过了modelsim 6.0 仿真，Quartue综合-Synchronous FIFO function, verilog language described by the modelsim 6.0 simulation, Quartue integrated