This is a use of Xilinx macroblaze the user program will read from flash memory...

verilog代码，串口发送接收代码，含有源代码和测试文件，准确可用(verilog code for serial port transmit and receive code, with source code and test files, and accurate available)

在quartus中使用IP核的实际例子与流程-The use of IP in the Quartus practical examples and nuclear flow

七段数码管显示数字时 使用VHDL语言编写(VHDL The seven-segment LED display digital clock)

the 8 bit alu by verilog

这是由阿龙利开发的程序，以控制ADC08D1000模拟 - 数字设备中的FPGA，赛灵思的Virtex-4 SX35 FPGA此处应用，DCM的用于控制FPGA中的时钟路径，所述时钟源是AD9517该PLC控制的FPGA中的串行端口

vga interface with text rom. font size 80x40. core need core regeneration.

LDPC COded OFDM System

说明：  LDPC码的FPGA实现，用verilog语言编写(FPGA implementation of LDPC code, written in Verilog language)

ep9351芯片的一个读取寄存器的测试程序，因为他的读取方式跟别的i2c设备不同，所以重新封装了一些i2c读写的接口。(one read ep9351 chip registers testing procedures, because he read i2c device with another different way, so repackaging some i2c interface to read and write.)

四位动态数码管显示数字时钟的分位和秒位。工具：Quartus ii 6.0 语言：VHDL-4 shows the number of dynamic digital tube digital clock and seconds bit. Tools: Quartus ii 6.0 Language: VHDL