由avalen总线转接i2c总线的vhdl程序 可应用于nios嵌入式系统

在Altera的FPGA开发板上运行第一个FPGA程序，以后我还会陆续发布这方面的代码-In Altera

QUARTER编程环境实现的智能洗衣机系统，通过DE0板子进行模拟，组要完成洗衣机5个步骤的顺序过程以及系统相应动作(QUARTER programming environment of intelligent washing system, through simulation DE0 board, groups 5 to complete the washing process and the system the sequence of steps corresponding action)

一个用Verilog编写的编帧、解帧及码速匹配的程序，相当经典-Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!

鉴于stm32在keil平台上的ADC采集转化，在LCD屏上显示程序(voltage acquisition adc)

MATLAB to HDL Code conversion

verilog实践 elc_clock 电子时钟设计(Verilog design practice elc_clock electronic clock)

dual port ram control (dual port ram control dual port ram control dual port ram control)

QuartusII8.0 Unix 和Linux按照指南-QuartusII8.0 Unix and Linux in accordance with the Guide

说明：  资料是本人根据相关文献资料用vhdl语言编写的旋转机械鉴相信号倍频的程序，multifre1.vhd是倍频程序，multifre1.vwf是仿真波形文件，stp1.stp是虚拟逻辑分析仪signaltap文件。该倍频程序可以直接使用，可以设置倍频数，修改实体参数N即可。(According to the literature data is the information I have written in with vhdl Rotating Machinery Kam believe that the procedure multiplier number, multifre1.vhd is the multiplier process, multifre1.vwf is the simulation waveform files, stp1.stp a virtual logic analyzer signaltap file. The multiplier process can be used directly, you can set the multiplier number, modify the parameter N can be solid.)

基于FPGA的VGA彩条显示 可用PAXplusII仿真-FPGA-based VGA color display available PAXplusII Simulation of