Synopsys 8051 IP core documentation.

CAN VHDL Code. Behavioral implementation of CAN bus interface.

VHDL examples for counter design, use QuickLogic eclips

自己写的FPGA实现电子琴的VHDL程序，曲目是两只老虎，用到一些模块，和片内存储间，呵呵(FPGA realization of his keyboard to write the VHDL program, tracks are two tigers, a number of modules used, and on-chip storage room, huh, huh)

基于verilog的cpri接口代码，支持各种速率自由切换，量产产品实际应用代码(Cpri interface based on verilog code, support various rate free switch, production products the actual application code)

给出了SVPWM算法的详细FPGA实现方法！(A detailed FPGA SVPWM algorithm to achieve the method!)

controller for sending serial data at different speeds

基于verilog的FIR滤波器程序设计（调试过的）-verilog

Quartus ii 入门基础 仅针对初学者 望各位童鞋们指导 呵呵 (Quartus ii entry basis only for beginners looking to guide their children' s shoes Oh you)

该程序实现多项式分数延迟（farrow）的设计。(The program polynomial fractional delay (farrow) design.)

此VHDL语言程序可以控制液晶屏幕任意动画播放(The VHDL language program can control the LCD screen any animation)