Synopsys 8051 IP core documentation.

本设计是基于FPGA的一个FIR低通滤波器设计，要求使用Verilog语言编写滤波器模块，通过编译和综合，并通过Matlab和modelsim联合仿真验证设计结果。(This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design results.)

通过vhdl实现ls138硬件功能 通过vhdl实现ls138硬件功能 -the description of ls138 in vhdl

LED based video wall tech spec

说明：  quartusii软件仿真实验代码 双二选一(quartusii software simulation code for a pair of two elections)

TFT 液晶屏显示，通过按键，显示不同的曲线(TFT LCD display)

全面了解Linux系统，构建服务器，用Vim写写程序(Fully understand the Linux system, build the server, write programs with Vim.)

verilog编写的ds18b20温度传感器程序，可综合(ds18b20 program written in verilog)

IIC控制器 for Sopc Builder-IIC controller for Sopc Builder

由avalen总线转接i2c总线的vhdl程序 可应用于nios嵌入式系统-By avalen bus adapter i2c bus VHDL program can be applied to Nios Embedded Systems

说明：  配置GTH ip的例子工程，选用7 series 芯片的GTH 113quad的四个通道，在程序中每个链路利用自己的恢复时钟进行数据解码，所以四个通道可以各自独立运行；成功工作在2.54Gb/s的链路状态，长时间（>24小时）的测试，误码率一直为0.(The GTH ip example project is configured with four channels of the GTH 113quad of the 7 series chip. Each link in the program uses its own recovery clock for data decoding, so the four channels can operate independently; the successful operation is at 2.54Gb/ The link state of s, long time (>24 hours) test, the bit error rate has been 0.)