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Tym605V2Demo
FPGA(赛灵思)试验箱 实验程序 有Audio,Buzzer,key,ledarray,ledseg.......(FPGA(赛灵思)试验箱 实验程序Audio,Buzzer,key,ledarray,ledseg)
- 2012-02-11 21:09:19下载
- 积分:1
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Lab15_sw2reg
开关数据加载到寄存器并显示的设计与实现.3. 设计一个可以把4个开关的内容存储到一个4位寄存器的电路,并在最右边的7段显示管上显示这个寄存器中的十六进制数字。我们使用到去抖动模块clock_pulse, 用btn[0]作为输入;8位寄存器模块,用btn[1]作为加载信号;7段显示管上的显示模块x7segbc;分频模块clkdiv,用以产生模块clock_pulse和x7segbc的clk190时钟信号。(Design of switching data is loaded into the register and display the.3. design and implementation of a 4 switch content storage circuit to a 4 bit register, and in the 7 section of the most on the right shows the register in the sixteen decimal digital display tube. We used to go to the jitter module clock_pulse, with btn[0] as the input 8 bit register module, as the loading signal by btn[1] 7 segment display module on the x7segbc pipe frequency module clkdiv, clk190 clock signal for generating module clock_pulse and x7segbc.)
- 2014-03-30 09:50:48下载
- 积分:1
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FSM
lap trinh FSM may trang thai
- 2014-10-22 15:56:39下载
- 积分:1
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emif_tt
实现dsp与fpga的emif的verilog异步实现,可实现异步读写以及相应功能模块控制,文件中包含仿真后的波形图形以及仿真测试程序,运行环境quartus ii11.0,仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)
- 2020-12-04 15:59:23下载
- 积分:1
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Mainly on the introduction MAGIC3000 series CPLD development board of the 10 exa...
主要介绍了关于MAGIC3000系列CPLD开发板的十个实例,如霓虹灯演示、与PC串口通信等。-Mainly on the introduction MAGIC3000 series CPLD development board of the 10 examples, such as neon demonstration, with the PC serial port communications.
- 2023-06-17 08:20:04下载
- 积分:1
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Verilog_golden
说明: 很好的免费学些 verilog教程
欢迎下载(Learn a good free download verilog tutorials welcome)
- 2009-08-02 14:45:56下载
- 积分:1
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USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including...
USB 1.1 PHY的代码,systemc语言 USB 1.1 PHY的代码,systemc语言,包括基于systemc语言的testbench ,和相关的doc文档-USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including systemc based testbench language, doc and related documents
- 2022-04-12 00:51:05下载
- 积分:1
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VHDL语言描述的二进制十进制译码电路,已经编译完成
VHDL语言描述的二进制十进制译码电路,已经编译完成-Binary decimal decoder circuit
- 2022-02-22 00:13:01下载
- 积分:1
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FIFO
Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)
- 2012-05-31 15:13:21下载
- 积分:1
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VHDL source code of the 100 cases, including the addition, subtraction, storage,...
VHDL的源码100例,包括加法、减法、存储、触发等,是初学者、开发人员的必备手册-VHDL source code of the 100 cases, including the addition, subtraction, storage, trigger and so on, is for beginners, developers must Manual
- 2022-06-28 13:10:26下载
- 积分:1