DDR SDRAM控制器的VHDL代码

RISC 5级流水线CPU，带HAZARD处理(RISC 5 pipeline CPU with HAZARD processing)

96x96 Digital MUX/DEMUX via SPI

TIMING LEARNING -TIMING LEARNING

全部通过，是我的精心设计，完全满足初学者的要求。0-99自动记数-all passed, I was carefully designed, fully meet the requirements of beginners. 0-99 automatic counting

一个vhdl实现的hamming码编码器-an hamming coder using vhdl

（1）距离算法研究和设计； （2）采用FPGA/CPLD实现。 -(1) distance algorithm and design (2) using FPGA/CPLD implementation.

原理图输入法制作的32位加法器。。。。。。。。(adder32)

VLSI based question set

说明：  fft代码,采用蝶形算法,包括C,matlab和verilog代码(fft code, using butterfly algorithm, including C, matlab and Verilog code)

64点的 FFT verilog,它是串行计算的，工作频率不到100M，计算速率很高，里面的层次很清晰。(64-point FFT verilog serial computing, the operating frequency of less than 100M, the calculated rate is high, the level inside is very clear.)