波动

使用matlab实现cdma 系统的rake接收机，比较最大比合并，等增益合并和选择性合并接收算法的性能(脢 鹿 脫脙matlab脢渭脧脰cdma 脧渭脥 鲁 渭脛rake 陆 脫脢脮 禄煤 拢 卢 卤 脠 陆 脧 脳 卯)

Xilinx 的DDR SDRAM控制器，用Verilog HDL描述- A DDR SDRAM contraller sample descripte in Verilog HDL ,base on Xilinx FPGA

FPGA实现反正切功能，工程原件，包括测试文件，能够很好实现该功能(FPGA implements arctangent function, original engineering)

一个用Verilog编写的编帧、解帧及码速匹配的程序，相当经典-Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!

有符号16位乘法器。经典booth编码。拓扑结构为wallance树。加法器类型是进位选择加法器。(Number system: 2 s complement Multiplicand length: 16 Multiplier length: 16 Partial product generation: PPG with Radix-4 modified Booth recoding Partial product accumulation: Wallace tree Final stage addition: Carry select adder )

说明：  基于FPGA的QPSK调制解调电路设计与实现 (QPSK)

关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL

qpsk调制解调，结果可以通过示波器进行观察(qpsk modulation and demodulation, the results can be observed by an oscilloscope)

基于FPGA的Verilog语言实现的六十进制计数器(FPGA-based Verilog language implementation of six decimal counter)

说明：  sd_sdram_lcd 是读取SD卡中的数据，然后通过LCD显示(It is to read the data in SD card and display it by LCD)