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dds
基于DDS和SOPC的谐波信号发射器,拥有可调节的频率,阶段和谐波比例的谐波信号发射器由本文所设计。(Based on DDS and SOPC harmonic signal transmitter, with adjustable frequency, phase and harmonic proportion of harmonic signal transmitter designed by this article.)
- 2016-04-26 09:21:50下载
- 积分:1
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Nexys-4-DDR-XADC
Nexys-4-DDR-XADC 开发板demo(Nexys-4-DDR-XADC e.v. Board demo)
- 2018-12-07 15:33:22下载
- 积分:1
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讲解用FPGA及其他芯片组成视频处理的电路设计和PFGA的程序的实现...
讲解用FPGA及其他芯片组成视频处理的电路设计和PFGA的程序的实现-Explain the use of FPGA and other video processing chips of the circuit design and FPGA realization of the procedure
- 2022-06-12 17:12:42下载
- 积分:1
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these files are written in verilog but i am uploading in text format
these files are written in verilog but i am uploading in text format
- 2022-02-06 16:09:07下载
- 积分:1
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DDR_interface
高速DDR存储器数据接口设计实例.
1. 将文件拷入硬盘
2. 产生DQS模块
3. 产生DQ模块
4. 产生PLL模块
5. 拷贝以上步骤生成的文件到子目录【Project】中
6. 打开子目录【Project】中的DataPath.qpf工程,设计顶层模块
7. 编译并查看编译结果
(High-speed DDR memory interface design data. 1. Copyed into the document hard disk 2. DQS generated module 3. Have a DQ module 4. Have a PLL module 5. Copies of the above steps to generate a document to a subdirectory 【Project】 6. Open the subdirectory 【Project】 DataPath.qpf in engineering, design top-level module 7. compilers to compile the results and see)
- 2009-04-27 11:52:56下载
- 积分:1
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很好的quartus软件仿真教程,flash版。
很好的quartus软件仿真教程,flash版。-Good quartus software simulation tutorials, flash version.
- 2023-03-08 19:40:06下载
- 积分:1
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Turbo Decoder Release 0.3
Turbo Decoder Release 0.3
* Double binary, DVB-RCS code
* Soft Output Viterbi Algorithm
* MyHDL cycle/bit accurate model
* Synthesizable VHDL model
-Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output
Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL
model
- 2022-01-30 12:47:05下载
- 积分:1
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52_divider
多倍(次)分频器
请注意:
本例的各个源描述的编译顺序应该是:
52_divider.vhd
52_divider_stim.vhd
(Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd)
- 2009-09-04 09:52:18下载
- 积分:1
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SPI的VHDL程序,经过quartus验证的,不错!
SPI的VHDL程序,经过quartus验证的,不错!-SPI of the VHDL program, after verification quartus, yes!
- 2022-12-07 04:00:03下载
- 积分:1
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这是我对FPGA程序的VME总线接口的设计,对FPGA的一面…
这是本人设计的一个关于VME总线接口的FGPA程序,FPGA一边连接ARM LPC2294,一边连接VME总线,FPGA采用的XILINX公司的SPARTANII系列,程序包包含完整的工程文件-This is my design of a VME bus interface on the FGPA procedures, FPGA side of the connection ARM LPC2294, while connecting VME bus, FPGA using the XILINX Inc. SPARTANII series, the package contains a complete project file
- 2023-01-09 16:20:04下载
- 积分:1