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Describes how to use VHDL language processor spi interface
介绍了如何用vhdl语言实现处理器的spi接口-Describes how to use VHDL language processor spi interface
- 2022-07-22 21:57:12下载
- 积分:1
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Verilog-Files---551
Programmable IIR Filter written in Verilog and its respective modules.
- 2014-05-30 03:46:09下载
- 积分:1
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高效的同步有限状态机的设计,本代码详细的说明了如何设计高效和规范的fsm设计...
高效的同步有限状态机的设计,本代码详细的说明了如何设计高效和规范的fsm设计-Efficient Synthesizable Finite State Machine Design using NC-Verilog
- 2023-07-18 00:50:02下载
- 积分:1
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13.3_Tracing
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动跟踪(System Generator based image processing engineering, multimedia processing on FPGA source, video-based motion tracking)
- 2020-11-04 17:39:51下载
- 积分:1
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HDL的例子源代码3 / 5
HDL example source code 3/5
jkff_a
- 2022-07-26 15:52:59下载
- 积分:1
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imports
说明: displayport 参考设计,可以对比自己工程做验证,另有参考设计XAPP1178未找到,采用方案为DP159 + Artix7 FPGA(xilinx displayport sink design)
- 2021-01-11 16:58:50下载
- 积分:1
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FPGA_LED
FPGA入门点亮一个LED灯,作为FPGA入门级程序(FPGA is)
- 2012-03-26 21:57:27下载
- 积分:1
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vga_graph_st
该程序用vhdl编写的vga显示的小游戏,到时屏幕上会显示一个小球,一根棒子,一面墙,棒子可以通过按键控制来移动。而小球在不停的运动,遇到墙会反弹。(Game written by the program with VHDL VGA display, the screen will display a small ball, a stick, a wall, stick to move through the key control. Ball in constant motion, encountered the wall will bounce.)
- 2013-05-18 21:01:23下载
- 积分:1
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10_ImageEdge
基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,图像边缘提取(System Generator based image processing engineering, multimedia processing FPGA implementation source code, image edge extraction)
- 2020-10-23 20:27:22下载
- 积分:1
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680605rece_7E
hdlc协议的相关程序,用verilog语言编写,供大家交流学习(hdlc protocol procedures using Verilog language for the exchange of learning)
- 2013-01-18 00:53:58下载
- 积分:1