基于EDA的八音自动播放电子琴设计 内有VHDL语言设计 有

说明：  Matlab to hdl code for Least_square testbench

(7,4)循环码的verilog编码程序，（7，4）循环码的verilog译码程序((7,4) cyclic code Verilog coding procedures, (7,4) cyclic code the verilog decoding procedure)

VHDL的基本程序，可以用来驱动键盘，功能强大，虽然和基础-VHDL

计算机组成原理课程设计代码，课程设计，计组(Computer organization principle curriculum design code, curriculum design, group calculation)

verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)

Run-Length Encoder Example: Input Sequence (hexadecimal format): 0A, 14, 14, 14, 14, 14, 14, 14, 56, 56, 56, 56, 56, 32, 32, 07 Output Sequence (hexadecimal format): 0A, 14, 87, 56, 85, 32, 32, 07

上传的是基于Xilinx的新出的开发板Zedboard的一个简单的知道文档，希望对有关同学有所帮助。(Uploaded a simple know the document based on Xilinx' s new development board Zedboard the hope that some of the students to help.)

Simulation and Synthesis Techniques for Asynchronous FIFO Design

说明：  1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 4. DESIGN FILE HIERARCHY 5. INSTALLATION AND OPERATING INSTRUCTIONS 6. SUPPORT

bch 编码和译码，用硬件语言vhdl实现(bch edcode and decoder)