登录
首页 » VHDL » DDS的频率转换可以以近似认为是即时的,这是因为它的相位序列在时间上是离散的,在频率控制字改变之后,要经过一个时钟周期之后才能按照新的相位增量增加,所以也可以说...

DDS的频率转换可以以近似认为是即时的,这是因为它的相位序列在时间上是离散的,在频率控制字改变之后,要经过一个时钟周期之后才能按照新的相位增量增加,所以也可以说...

于 2022-02-13 发布 文件大小:2.00 MB
0 178
下载积分: 2 下载次数: 1

代码说明:

DDS的频率转换可以以近似认为是即时的,这是因为它的相位序列在时间上是离散的,在频率控制字改变之后,要经过一个时钟周期之后才能按照新的相位增量增加,所以也可以说它的频率转换时间就是频率控制字的传输时间,-DDS frequency conversion can be considered similar to real-time, this is because it is the phase sequence in time is discrete, in the frequency control word change after one clock cycle to go through before a new phase in accordance with the incremental increase, so it can be said of the frequency switching time is the frequency control word transmission time,

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • TFT_CTRL_800_480_16bit
    说明:  文件用于驱动TFT屏,分辨率800*400,平台为quartus13,芯片为cycloneIV(The file is used to drive the TFT screen with a resolution of 800*400. The platform is quartus 13 and the chip is cyclone IV.)
    2019-04-12 09:22:29下载
    积分:1
  • powerlink开源的最新全部源码
    powerlink最新的开源全部VHDL及C/C++代码,用于powerlink的开发。是当前最新版本。包含Linux的实现及nios /arm软核的实现。可以用于xinx和Altera的FPGA。
    2022-07-10 04:47:40下载
    积分:1
  • include UART port of VERILOG source, the program tested in FPGA, as chip design,...
    包含UART口的VERILOG源程序,该程序在FPGA上验证通过,可作为芯片设计,或FPGA设计的一个完整IP核,硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
    2022-06-01 13:44:15下载
    积分:1
  • intelmirco
    INTEL 微处理器 第八版 答案 从第二章开始,奇数偶数的答案都有。(INTEL microprocessor eighth edition answer from the beginning of the second chapter, the answer has odd and even.)
    2021-01-19 02:38:43下载
    积分:1
  • vhdl 语言实现Rs232
    Altera DE2 上使用 vhdl 语言设计 RS232 控制器。这是一个串口模块可用于嵌入系统。
    2022-03-09 23:32:48下载
    积分:1
  • CODE_VHDL_INITIALIZING 液晶电视 DISPLAY(KHỞI TẠO HIỂN THỊ LCD)
    CODE_VHDL_INITIALIZING 液晶电视 DISPLAY(KHỞI TẠO HIỂN THỊ LCD)
    2022-03-17 18:12:45下载
    积分:1
  • TCD1304_drive
    FPGA驱动TCD1304AP线阵CCD,并经采集将数据通过串口传输至上位机(FPGA drives TCD1304AP linear CCD, and by collecting the data transmitted through the first bit machine serial)
    2021-05-15 18:30:02下载
    积分:1
  • 基于EPM1270的PS2键盘鼠标驱动源码Verilog
    基于EPM1270的PS2键盘鼠标驱动源码Verilog-Based on the EPM1270 the PS2 keyboard and mouse-driven Verilog source
    2023-04-28 06:25:04下载
    积分:1
  • RTC
    verilog编写的RTC(实时时钟)包含APB总线接口、时钟计时部分等(verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other)
    2009-12-19 23:51:50下载
    积分:1
  • UART
    UART文件 包括发送器 接收器 fifo 测试文件(UART file includes a receiver transmitter fifo test files)
    2016-06-06 20:35:02下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载