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CPU
使用QuartusII软件,利用VHDL语言设计实现CPU,其中包含时序图仿真。(Using software QuartusII, using VHDL language to design the CPU, which contains sequence diagram simulation.)
- 2015-07-22 16:23:52下载
- 积分:1
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用VHDL语言设计四位全加器,有低位进位和高位进位。
用VHDL语言设计四位全加器,有低位进位和高位进位。-VHDL language with four full-adder design, there are low and the high binary binary.
- 2022-03-20 15:03:38下载
- 积分:1
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rc-evga-indtube
evga-indtube.h - Keytable for evga_indtube Remote Controller.
- 2015-04-16 11:06:12下载
- 积分:1
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用VHDL编写的EPP通信协议,可以同时收发字节
用VHDL编写的EPP通信协议,可以同时收发字节-EPP written in VHDL, communication protocol, you can also send and receive bytes
- 2022-05-22 02:38:48下载
- 积分:1
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非常好的SDRAM Controller 设计文档。工程必备
非常好的SDRAM Controller 设计文档。工程必备-SDRAM Controller Design of a very good document. Works required
- 2023-08-30 16:25:04下载
- 积分:1
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BmpDecoder
适用于Altera FPGA Nios II平台uClinux OpenCV之BmpDecoder的源码(Souce code of BmpDecoder for Altera FPGA Nios II uClinux OpenCV)
- 2011-02-11 16:43:45下载
- 积分:1
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四VHDL模块的家庭,已经过测试,在ISE8.1通过
四位全家器的VHDL语言模块,已经在ISE8.1上经过测试通过-family of four VHDL modules, has been tested on ISE8.1 through
- 2022-03-21 16:25:17下载
- 积分:1
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ber_tester_m
基于FPGA的误码测试仪 (已注释)
--锁相环-M序列生成模块--数据接口模块-
--模拟信道模块---本地M序列生成模块--同步模块--误码统计模块--显示模块-(FPGA-based BER tester)
- 2020-10-28 11:39:58下载
- 积分:1
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ZedBoardyuanlitu
zedboard原理图详细,PCB板焊接方便,每个接口表明清楚。(Zedboard schematic in detail, PCB board welding is convenient, each interface that clearly.)
- 2017-01-03 20:07:20下载
- 积分:1
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CJQ-V1.0-fpga
实现FPGA对AD芯片AD7060的控制,程序代码的注释很多,易学易懂,适合初学者学习使用(it is good ...)
- 2013-10-10 11:20:31下载
- 积分:1