用VHDL编写的EPP通信协议，可以同时收发字节

一个vhdl实现的hamming码编码器-an hamming coder using vhdl

---------------------------------------------------------------------------------- -- Company:       VISENGI S.L. (www.visengi.com) - URJC FRAV Group (www.frav.es) -- Engineer:      Victor Lopez Lorenzo (victor.lopez (at) visengi (dot) com) -- -- Create Date:    12:39:50 06-Oct-2008 -- Pr

IIC主设备的代码实现（verilog),从设备模型-IIC main equipment of the code (verilog), from the device model

INTEL 微处理器 第八版 答案 从第二章开始，奇数偶数的答案都有。(INTEL microprocessor eighth edition answer from the beginning of the second chapter, the answer has odd and even.)

用VHDL语言实现了DES加密算法，其中包含了测试程序，能够进行仿真。(Using VHDL language implementation of the DES encryption algorithm, which contains the test procedures can be simulated.)

该程序设计了一个产生PCM码流时序信号的模块，他包括输入端CLK，SET及输出端Q1,Q2,Q3-the program have designed a PCM signal timing modules, including the CLK input, and output SET Q1, Q2 and Q3

实现dds功能，利用quartus软件， 子模块包括加法器，锁相环，date-rom 利用原图将各模块综合，利用ps2键盘控制频率及相位。-Dds realize functions, using Quartus software, sub-modules including the adder, phase-locked loop, date-rom image to the module using integrated, using ps2 keyboard to control the frequency and phase.

采用STC89C52单片机的定时器以实现两路PWM波输出，占空比、频率可调(Microcontroller timer used to achieve STC89C52 two PWM wave output, duty cycle, frequency adjustable)

这是一个HDB3的译码器，实现从HDB3双极性码到高低电平二值序列的转化-This is a decoder of the HDB3, HDB3 bipolar from high-low-level code to the conversion of binary sequences

说明：  简单流水线CPU，使用 verilog实现，实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)