4x4 electronic locks central control system. Six input control.

HDLC控制器源码，包括单独HDLC的Tx端和Rx端实现，以及顶层带FIFO和Wishbone总线控制器的实现，通过Wishbone可方便与CPU连接，通过软件控制整个HDLC控制器的工作。

该代码完成了利用IIC总线接口，对HDMI芯片的EDID码进行配置的功能，已经验证在XILINX ML605开发板可用。

it shows bcd counter

代码来源http://www.spacewire.co.uk/video.html，需要CRT显示ITU.656格式的视频的可以参考

RAM读写控制器，用verilog实现的简单易懂的RAMROMsram控制核-Controller RAM read and write, using verilog implementation of easy-to-understand control of nuclear RAMROMsram

本文档对quartus与modelsim运用操作描述十分详细，对初学者，会有很大帮助！(Quartus and modelsim this document on the use of operations described in great detail, for beginners, there will be a great help!)

本程序是在Quartus7.2环境下编译的一个简单的(2,1,3)卷积码，能够成功地编译和仿真。(This procedure is in circumstances Quartus7.2 compile a simple (2,1,3) convolutional code, can successfully compile and simulation.)

SHIFT_8REG是8位的一个具有移位功能的寄存器，每一次数据打入都会从这个寄存器的最低位打入，并相应进行向左移位。 ODD_110BREG是一个3位的备份寄存器，寄存器中存放的是奇数帧的同步头，也就是110。 EVEN_9BHREG是一个8位的备份寄存器，寄存器中存放的是偶数帧的同步头，也就是10011011。这两个寄存器的初始值在系统一开始就打入。 -SHIFT_8REG is eight with a displacement of the functional Register, Each will enter the data from the register into the lowest point, and the left shift accordingly. ODD_110BREG is a three backup Register, the Register is stored in the odd frame synchronization head, is 110. EVEN_9BHREG 8 is a backup Register, which register is kept even the first frame synchronization, is 10011011. This register the two initial value of the system into a start.

说明：  一个PN序列发生器，大M序列，供参考学习，(A PN sequence generator, the M series, for reference study,)

SDRAM控制器 带仿真模型文件 仿真通过(Simulation model file simulation through SDRAM controller)