IIC EDID码配置

此实验例程适用于Actel Flash架构的ProASIC3/E系列FPGA，适合于FPGA及Verilog HDL的初学者，配套EasyFPGA030开发套件。-Routine application of this experiment in the Actel Flash architecture ProASIC3/E series FPGA, fit in the FPGA and Verilog HDL for beginners and supporting development kit EasyFPGA030.

verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)

dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies

SOPC基于MATLAB与DSP Builder设计技术 实验使用说明，非常详细，易于上手(dsp builder)

VHDL语言基本数学运算库-VHDL basic arithmetic library

基于FPGA的DDS信号源设计，32位相位累加器，产生可调频率(FPGA-based DDS signal source design, 32-bit phase accumulator to generate tunable frequency)

Verilog 写的HDMI接口源程序及说明文档(HDMI interface verilog code and specificaiton paper)

说明：  CPU课程设计要求以FPGA开发平台为例，分析 CPU 设计的流程与仿真。 本次开发使用的硬件描述语言是 Verilog 语言，使用的指令系统是一个以 MIPS 指令集为子集的指令系统，共 22 条指令，所用的设计仿真软件Modelsim。(CPU curriculum design requires FPGA development platform as an example to analyze the process and Simulation of CPU design. The hardware description language used in this development is Verilog language, and the instruction system used is an instruction system with MIPS instruction set as a subset, with 22 instructions in total. The design simulation software Modelsim is used.)

产生高斯最小相移键控信号的阐述仿真，包括调制解调、信道模型等。(Simulation program to realize GMSK transmission system)

卫星信道模拟器能够模拟卫星信道的传播特性，用于设备的通信调试，节 约研发成本。目前，很多卫星信道模拟器在参数设置上存在问题：有的参数难 以调节；有的采用上位机进行参数设置，通过上位机设置参数需要连接电脑， 适应性差。针对上述问题提出了一种基于FPGA可触控卫星信道模拟器，FPGA 作为算法实现和控制单元，通过控制触摸屏方便快捷的实现参数设置。(Literature of Satellite Channel Simulation Based on FPGA)