Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核...

8051的verilog内核，fpga里实现8051的话用得上-8051 Verilog cores, fpga achieve useful 8051 words

基于FPGA的成型滤波器的代码，里面内附激励文件，使用verilog编写(FPGA-based shaping filter code, which included incentives files using verilog write)

说明：  2020 XILINX Vivado ISE IP License最全最可靠License获取方式。 LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MAC 50G Enthernet MAC 100G Enthernet MAC RS Encoder/Decoder Display Port/ DP Video Test Pattern Generator RapidIO tri mode ethernet mac(LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MAC 50G Enthernet MAC 100G Enthernet MAC RS Encoder/Decoder Display Port/ DP Video Test Pattern Generator RapidIO tri mode ethernet mac)

四轴动力模块，用一个顶模块控制，输入有：油门（20档）；指令；水平仪控制指令，4个输出口(Axis power modules, with a top module control inputs are: accelerator (20 files) instruction Level control instructions, four output ports)

使用vhdl语言在altera公司的up3板上产生vga信号，里面有详细的解析和说明，是一个很好的教程。-use of the VHDL language ALTERA company"s board up3 have vga signal containing a detailed analysis and explanation is a good guide.

说明：  demo6 蜂鸣器实验 蜂鸣器演奏音乐(demo6 buzzer buzzer experiment playing music)

基于altera公司MAX10型FPGA的ADC调试程序(ADC-based debugger altera company MAX 10 type of FPGA)

乒乓RAM静态随机存储器的控制，用于解决数据流连续存储问题。(Ping pong RAM static random access control, to solve the problem of continuous data flow storage.)

彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)

FPGA核心板EP4CE10F17C8电路原理图(Circuit schematic diagram of EP4CE10F17C8 core board of FPGA)