9. For the key to enter a password lock, assuming that reset after the seven lam...

verilog 的东西好好用的呢，那是verilog 学习者的必备东西哦(verilog things properly used it, it is an essential learners verilog things oh)

lacp代码，可以参照学习Lacp协议的相关状态机等知识(LACP code, can refer to the relevant state machine learning knowledge of Lacp protocol)

完成一个1位全减器的设计。以全减器为元件程序完成8位减法器设计。(Completed a one minus the whole design. Full reduction is to complete eight subtraction element program design.)

statemachine project for my school

VHDL implementation of RC6 encryption algorithm Test file represent applying all zero input and all zero key note that result is correct but bytes positions are swapped

标准SDR SDRAM控制器参考设计，Lattice提供的verilog源代码-standard SDR SDRAM controller reference design, the Lattice Verilog source code

用于实现fpag-cpu的数据通路源代码。用vhdl编写，包括内存，寄存器组，和alu（简陋的alu，仅包含加法器）三大部分通过手动微指令输入信号，可以往内存写入数据，并加载到寄存器组中，通过alu产生结果，结果保存在一个锁存器中，可以把结果写回寄存器组或者内存。本人在quartus下编写仿真通过。附件中未给出相关工程文件。

自己编的一个分频器的程序模版 虽然原理很简单，经过多次实践很实用 被多次用在其它的程序中-own series of the dividers of a procedure template Although very simple principle, after repeated practice by many very practical use in other proceedings, and,

altera 官方rs232例程 很详细很实用-official rs232 routines in great detail altera very practical

用verilong hdl语言编写的数据采样程序，A/D采用的是TLC5260-Verilong hdl language used data sampling procedures, A/D using the TLC5260