用vhdl来实现的数字频率合成的技术，几乎很全的，所有的都有...

说明：  ucos II 中文手册额，可以学习一下哦(UCOS II Chinese manual volume, you can learn it)

本程序实现两个整数平方和相加并且输出结果-the program two integers and the sum of squared output

该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码，会用QUATUSII的人都应该知道如何使用，希望能给你带来帮助-The project is based on the language verilog hdl frame transmission protocol HDLC frame of this generation- Codes will be used QUATUSII people should know how to use, in the hope of giving you helpful

本例为电子琴VHDL程序原代码,电子琴,可实现基本功能-In this case the procedures for organ VHDL source code, organ, can realize the basic functions of

用VHDL语言实现QPSK调制功能和解调功能,(Using VHDL language features QPSK modulation and demodulation functions,)

在Altera开发板上实现RS232串口通信，平台为CycloneII，可通过QuartusII软件修改引脚移植到其它平台(Realize RS232 serial communication on Altera development board, platform for CycloneII, through software QuartusII modify pin portable to other platforms)

logic lock 的vhdl源码，altera平台适用。-logic lock the VHDL source code, altera platform.

最新的CCSDS高光谱图像压缩算法标准的FPGA实现，用VHDL实现的。可参考。绝对物有所值，希望对你的设计有所帮助!

7段数码显示译码器-seven of the digital display decoder

用verilog 语言实现七人投票表决器(verilog seven voting)