曼彻斯特编解码 Xilinx提供的VHDL的源代码

Synchronous DRAM (SDRAM) has become a mainstream memory of choice in embedded system memory design due to its speed, burst access and pipeline features. For high-end applications using processors such as Motorola MPC 8260 or Intel StrongArm, the interface to the SDRAM is supported by the processor’s built-in peripheral module.

FIFO的verilog描述(Verilog description of the FIFO)

8 bit cpu vhdl design code not tested

一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code

uart16550 ip core 通用异步收发器vhdl源代码-uart16550 ip core UART VHDL source code

German REAL LPT! USB2LPT

csapp 第二版 体系结构实验 答案 第三个部分能跑58分(the second edition csapp architecture experiment the third part of the answer can run 58 minutes)

《Verilog HDL 程序设计教程》5-"Verilog HDL Design Guide" 5

说明：  用VERILOG语言实现的频谱分析仪（FFT)(VERILOG language with the Spectrum Analyzer (FFT))

LDPC码不同码长对比。码率选择1/2.码长分别为256，512，1024.(LDPC codes of different code length contrast. Bitrate select 1/2 yards long were 256,512,1024.)