RiscCpu

具有16个校验位的RS编码器，在FPGA上实现。(With 16 RS encoder, the parity bit in the FPGA.)

Eliminate the program of key bounce

RS（255，223）编码器，已实际运用到产品中(RS (255,223) encoder has actually applied to products)

HDL example source code 1/5 tff_a

高速高性能FFT处理器的VLSI实现研究，适合做FPGA的技术人员参考研究FFT-High-speed high-performance FFT processor VLSI realization of research, suitable for FPGA technology reference study FFT

FPGA实现DSP的Verilog 示例(FPGA realization of DSP-Verilog Example)

GAL16V8(仿真74LS138),试验通过。包括able及jed文件。对pcb印板设计时，对简化走线特别有用。简单的修改GAL16V8程序，可灵活地进行地址译码修改。(GAL16V8 (simulation 74LS138), test passed. Including the able and jed file. Printed on the pcb board design, especially useful to simplify alignment. Simple modifications GAL16V8 program, the flexibility to change the address decoding.)

这个是用verilog语言编写的基于FPGA的交通灯控制器，分别控制四个方向上的交通灯的通断-The verilog language is FPGA-based traffic light controller, respectively, the four direction control of traffic lights-off

FPGA控制的SRAM接口不分的设计-FPGA-controlled SRAM interface design, regardless of

用于测试ACEX1k30的流水灯程序，晶振频率为20mhz。运行环境Maxplus2-for testing the water ACEX1k30 lights procedures, the frequency of 20MHz crystal oscillator. Operating environment FLEX10K