次源码实现一个扩频接收机系统，用VHDL语言编写，并且有完整得测试程序

一种合并频率的方法对时频分析及其有用所以才上传(a fast combination)

Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)

32位元浮点数加法器,用于以VHDL编写的32位元CPU-32 bits floating-point Add

16X2液晶显示屏的FPGA显示驱动设计。-16x2 LCD display driver design of the FPGA.

本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.

说明：  具有计时 设置时间 闹钟 秒表 功能的数字钟设计 外设矩阵键盘(Digital clock design peripheral matrix keyboard with the function of timing setting time alarm clock stopwatch)

基于VHDL语言编写，可下载到FPGA板子上实现的cordic算法实现的设计，并用该算法实现sin和cos的计算，计算结果显示在数码显示管上，已包含按键防抖动功能的实现。(Based on VHDL language, can be downloaded to the the cordic algorithm implemented in the FPGA board to achieve the design and calculation of sin and cos using this algorithm, the results displayed on the digital display tube is included on the function of the realization of the button shake.)

说明：  Laplace可以应用于图像的锐化，根据其原理，对于Laplace后的图像同样可以进行边缘检测。(Laplace can be applied to image sharpening. According to its principle, edge detection can also be performed for images after Laplace.)

说明：  ddr2原理图设计，原厂电路图设计，很好很强大 16bit(ddr2 schematic design, the original schematic design, a very powerful 16bit)

代码基于VHDL语言的个文化代码有用的但是可能有错误下在是倾销心-VHDL code based on the cultural code useful but may be under the wrong heart is dumping