BCH编码器和解码器的源代码，FLASH控制器，通信是必要的哦

说明：  简单流水线CPU，使用 verilog实现，实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)

用Vrilog产生一个混沌信号，并用MATLAB仿真，画出波形。(With Vrilog generate a chaotic signal simulation using MATLAB, draw the waveform.)

FFT程序，此程序虽然耗逻辑资源很大，但是在接受数据后的第7个时钟沿就可以输出FFT变换后的数据，对要求时延较低的系统可以考虑-FFT procedure, this procedure should not consume a lot of logic resources, but the data in the first seven clock can be output along the FFT transformed data, the requirements of time-delay system can be considered lower

在电子产品中，加法器是一种数字电路，执行加法的数字。在许多计算机和其他种类的处理器，加法器使用不仅在算术逻辑单元（s），而且其他地方的处理器，

1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 4. DESIGN FILE HIERARCHY 5. INSTALLATION AND OPERATING INSTRUCTIONS 6. SUPPORT

vhdl编写的硬件乘法器-prepared by the VHDL hardware multiplier

利用xilinx开发板，使用嵌入式系统，编写的ps2键盘和利用dds原理产生正弦波的程序(Using xilinx development board, the use of embedded systems, the preparation of the ps2 keyboard and use the procedures dds elements of the sine wave)

基于研华采集卡的FIFO双缓存区高速数据采集(FIFO DAQ)

说明：  基于FPGA设计的串口发送及接收程序，波特率可调(FPGA - based serial port sending and receiving)

TDM，就是时分复用。本程序完成4通道，没通道最多32路64K信号的交换，就是说可以完成32x4个电话信号交换(TDM, is time-division multiplexing. The process is complete 4-channel, no channel up to 64K 32 to exchange signals, that can be done 32x4 telephone signal exchange)