BCH编码器和解码器的源代码，FLASH控制器，通信是必要的哦

通信系统帧同步信号的设计与实现，巴克码识别器系统完整VHDL程序，本人课程设计，完全能正常运行，程序运行环境为Quartus II 7.2 (32-Bit)，win7系统。编译码模块、分频模块、门限设置模块、仿真电路和程序都有。相互交流，共同学习！！

基于8B10B的编解码模块的设计，使用verilog HDL语言，具有实用价值。(8B10B encoder)

本源码为Nios II的开发示例,主要演示Nios II的定时中断器的应用。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II interrupt timing device applications. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.

一个SDH中最基本传输模块STM-1的帧头检测器，verilog编程实现-A basic SDH transmission module STM-1 Header detector, verilog Programming

在几乎所有的数字系统，计数器被广泛使用的领域，如频率

Vhdl实现的鼠标协议历程，代码可读性高，适合作为案例参考。-VHDL realize the course of the mouse protocol, code readable, suitable as a reference case.

VHDL之二進制轉BCD碼之程式碼，算完整的(Of binary to BCD code VHDL code, operator complete)

i2c总线的工程实现，可以用在altera环境下验证-i2c bus project implementation can be used in altera verification environment

-- State machine for reading data from Dallas 1621 -- -- Testsystem for i2c controller--- State machine for reading data from Dall as 1621---- Testsystem for i2c controller

FPGA驱动TCD1304AP线阵CCD，并经采集将数据通过串口传输至上位机(FPGA drives TCD1304AP linear CCD, and by collecting the data transmitted through the first bit machine serial)