BCH编码器和解码器的源代码，FLASH控制器，通信是必要的哦

电子打铃器 在max plus 2 下编译通过-electronic bell playing for the max plus 2 under through compiler

用VHDL编写的huffman编码的源程序(With the VHDL source code written in huffman coding)

emWin 在LPC2478上实现LCD的高性能显示(emWin to achieve high-performance LCD display in the LPC2478)

说明：  mojo v3 complete eagle schematic

This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the

When the initial input falls between the Switch off point and Switch on point values, the initial output is the value when the relay is off.

bch 编码和译码，用硬件语言vhdl实现(bch edcode and decoder)

verilog for full_adder

使用VHDI Dispaly字符。显示了一个模拟的正常工作的LCD控制器硬件实现。这种模拟演示了不同的状态机协同工作的方式。作为初始化序列完成时，主状态机的命令的状态开始。

说明：  QPSK的解调程序，采用Verilog编写而成(QPSK demodulation program, written by Verilog)