这个程序是基于等精度测频原理的频率计，用VHDL语言实现，频率测量测量范围1~9999；用4位带小数点数码管显示其频率，并且具有超量程、欠量程提示功能。...

Ethernet MAC-MII interface of Transmit

产生VGA彩条信号(Verilog 语言）-Generate VGA signal

开发系统上采用的时钟信号的频率是20MHz，可分别设计计数器对其计数，包括计秒、分、小时、日、周、月以及年等。在每一级上显示输出，这样就构成了一个电子日历和时钟的模型。为了可以随意调整计数值，还应包含设定计数初值的电路-Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes an electronic calendar and clock models. Can also adjust the order value, should also be included in setting the initial count circuit

企业用verilog代码风格规范 本规范规定了IC设计项目开发过程中VerilogHDL源代码的编写总则、要求及模板文件。(Enterprises with verilog code style guide for the preparation of this specification General IC design project development process VerilogHDL source code, requirements and template files.)

该程序实现最小频移键控信号的调制解调，经测试无误。(The program implements minimum shift keying signal modulation and demodulation, tested and correct.)

说明：  能实现输入0.5 1 5块钱的累加，然后对应购买的商品价格进行比较，显示找的钱数或错误灯(MY English is very good)

各种常用模块的VHDL描叙实例，PDF格式-various modules used VHDL depicts examples, PDF format

使用ALTERA上DE2平台，使用Verilog描述，交通灯控制。-Using ALTERA on DE2 platform, use the Verilog description of the traffic light control.

基于FPGA的1024点流水线工作方式的FFT实现,适合fpga的技术人员做信号处理参考-FPGA based on the work of the 1024-point pipelined FFT approach the realization of the technical staff for doing fpga signal processing reference

powerlink最新的开源全部VHDL及C/C++代码，用于powerlink的开发。是当前最新版本。包含Linux的实现及nios /arm软核的实现。可以用于xinx和Altera的FPGA。