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功率门控IEEE论文可为IP核的实现充分利用
ieee paper on power gating and can be use full for implementing on ip core
- 2022-02-03 18:58:04下载
- 积分:1
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dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
- 2022-11-12 18:25:03下载
- 积分:1
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用vhdl语言 来实现 四位并行加法器的功能 是本科生的必学内容...
用vhdl语言 来实现 四位并行加法器的功能 是本科生的必学内容-Using VHDL language to realize four parallel adder function is a must for learning the content of undergraduate
- 2022-05-12 13:50:07下载
- 积分:1
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一款8位Turbo
一款8位Turbo-51的CPU软核的设计-An 8 Turbo-51" s soft-core CPU design ....
- 2022-02-25 13:52:11下载
- 积分:1
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Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB
Xilinx,Altera,ARM,AVR,S52,Lattice等系列FPGA的下载线电路图和PCB-Xilinx, Altera, ARM, AVR, S52, Lattice series FPGA download cable circuit diagram and PCB
- 2022-03-17 00:48:42下载
- 积分:1
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irda.tar
depends on irda transmitter recever
- 2009-11-20 00:31:48下载
- 积分:1
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performance-of-pcie
本白皮书探讨了在PCI Express的因素
技术可能会影响性能。它还
提供指导如何估算
的系统性能。(This white paper explores the factors in PCI Express technology may affect performance. It also provides guidance on how to estimate the system performance.)
- 2013-10-29 10:52:43下载
- 积分:1
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dianzhen
fpga实验板上16*16点阵显示汉字的程序-翻译结果fpga实验板上16*16点阵显示汉字的程序(Experimental fpga board 16* 16 dot matrix display Chinese program- translation results fpga experimental board 16* 16 dot matrix display Chinese characters in the program)
- 2013-12-24 16:28:00下载
- 积分:1
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看了好多网了,发现有2to4译码,3to8译码,今天我要用4to16译码,写完了就发了上来...
看了好多网了,发现有2to4译码,3to8译码,今天我要用4to16译码,写完了就发了上来-saw a lot of net and found 2to4 decoding, 3to8 decoding, today, I must 4to16 decoding, finished on the fat in the ranks
- 2022-03-09 18:15:27下载
- 积分:1
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本文件是用CPLD(EPM7064)驱动线阵CCD(ILX509),其中包括原理图和程序...
本文件是用CPLD(EPM7064)驱动线阵CCD(ILX509),其中包括原理图和程序-This document is a CPLD (EPM7064) driver line array CCD (ILX509), including schematics and procedures
- 2022-02-12 02:58:13下载
- 积分:1