verilog写的数字频率计的选择模块,用与显示的选择

说明：  难得的soc设计用的ddr3 verilog，可用于学习！！！！！有datasheet ，可仿真(soc ddr3 verilog for study !!)

如果不考虑占空比，直接利用计数器来进行分频，则占空比会发生变化。下面程序实现1：1的三分频。-if not duty cycle directly counter to the use of sub-frequency, duty cycle will change. Below a program : a third of the frequency.

PCI vhdl for Fpga designer to design PCI IP

有单极倍频功能的matlab spwm逆变器(Unipolar multiplication function the the matlab spwm of inverter)

vhdl经典实例――信号灯控制，入门者必须掌握-vhdl classic example-- to control lights, beginners must master

altera的几种新型的FPGA的配置方法和使用心得-altera several new FPGA configuration methods and the use of experience

System Verilog for design verification

说明：  控制步进电机转动，正反转，旋转角度完美掌握。很好用，亲测(Control stepping motor rotation, positive and negative rotation, perfect control of rotation angle. Very easy to use, personal test)

有很多例子及测试代码，对初学者很有帮助，很容易上手-a lot of examples and test code, useful for beginners, it is easy to get started

Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由(Xilinx FPGA timing constraint information, original, classic no reason)