verilog写的数字频率计的选择模块,用与显示的选择

James Armstrong VHDL Design , source code

verilog 教程 PPT版本 语法 结构 设计技巧等(Verilog tutorial PPT version)

忆阻器的SPICE建模模型说明及仿真结果说明(Memristor SPICE modeling and simulation results show that the model describes)

fpga debounce filter code in vhdl

EKG SIGNAL PROCESSING THROUGH CORDIC

基于FPGA的AD转换控制器设计，AD7822，quartus II，verilog hdl(A Design of the A/D Convertion Control Module Based on FPGA)

设计遥控器接收解码电路。该电路接收编码后的串行数据，解码输出数据。电路接收 到的串行数据的格式为： 4 位同步码“ 1010”， 4 位数据（高位在前）， 1 位奇校验码（对前 8 位数据校验）(Design of remote control receiver decoding circuit. The circuit receives the encoded serial data and decodes the output data. The format of the serial data received by the circuit is: 4 bit synchronous code "1010", 4 bit data (high in the front), 1 bit parity check code (check for the first 8 bits of data))

二进制转十进制BCD码 Verilog语言 quartusII(Binary to decimal BCD code Verilog language quartusII)

DS18B20温度传感器，用verilog语言实现(DS18B20 temperature sensor, with the verilog language)

verilog实现的FPGA三态以太网链路层通信代码，里面有状态机，并按各个模块的功能分了文件夹，还有说明文档，自定义帧的产生和接收，开发环境为Xilinx ISE，测试无误。(verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well as documentation, self-defined frame generation and reception, the development environment for the Xilinx ISEtest and correct.)