登录
首页 » VHDL » vhdl classic example

vhdl classic example

于 2022-06-02 发布 文件大小:176.33 kB
0 183
下载积分: 2 下载次数: 1

代码说明:

vhdl经典实例――信号灯控制,入门者必须掌握-vhdl classic example-- to control lights, beginners must master

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • FPGASquare-RootRaised-CosineFilter
    数字通信系统中, 基带信号的频谱一般较宽, 因此 传递前需对信号进行成形处理, 以改善其频谱特性,使 得在消除码间干扰与达到最佳检测接收的前提下,提高信道的频带利用率。目前,数字系统中常使用的波形成形滤波器有平方根升余弦滤波器、 高斯滤波器等。设计方法有卷积法或查表法, 其中: 卷积法的实现,需要消耗大量的乘法器与加法器,以构成具有一定延时的流水线结构。为降低硬件消耗,文献提出了一种分(FPGA Implementation of Square Root Raised Cosine Pulse Shaping Filter)
    2011-05-04 21:23:36下载
    积分:1
  • The source code for the Nios II development of an example, the main demonstratio...
    本源码为Nios II的开发示例,主要演示Nios II的定时中断器的应用。开发环境QuartusII。 本示例十分经典,对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II interrupt timing device applications. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.
    2022-03-20 14:56:37下载
    积分:1
  • adconfig
    AD9268的配置Verilog实现,程序用于实现4通道的AD9268的配置(The 4 channel AD9268 configuration)
    2021-04-15 16:58:54下载
    积分:1
  • jiaotongdeng
    十字路口交通灯的单片机控制源代码 红黄绿三灯 还有数码管时间显示(Intersection traffic lights SCM source code red yellow three lights and LED time display)
    2011-08-07 23:34:04下载
    积分:1
  • clock
    本程序实现数字钟系统,有整点报时功能,可显示切换年月日,定时功能(Digital clock system of this program, with the whole point timekeeping function, can display the date, the timing function)
    2015-04-19 22:07:02下载
    积分:1
  • 用verilong hdl语言编写的数据采样程序,A/D采用的是TLC5260
    用verilong hdl语言编写的数据采样程序,A/D采用的是TLC5260-Verilong hdl language used data sampling procedures, A/D using the TLC5260
    2023-04-01 09:25:04下载
    积分:1
  • tsobbellh
    这是我本人自己开发的可用于256*256大小的图像进行sobel边缘检测的vhd文件,可在QuartusII或MaxplisII下综合与与仿真,并在FPGA上测试过。能进行修改支持其他大小图像的sobeel边缘检测,同时还能实现其它的图像模块化处理算法,例如高斯滤波,平滑等。 (This is my own development vhd file, can be used for 256* 256 size image sobel edge detection under QuartusII or MaxplisII synthesis and with simulation, and tested on FPGA. Can be modified to support other sobeel size image edge detection, while still achieving other image the modular processing algorithms, such as Gaussian filtering and smoothing.)
    2012-08-23 22:17:19下载
    积分:1
  • EP2C70F896C6N-pins
    将VHDL程序下载到DE2开发板,引脚分配时需要知道的芯片每个引脚功能(VHDL program will be downloaded to the DE2 development board, you need to know when the pin assignments for each pin of the chip functions)
    2020-12-09 11:09:21下载
    积分:1
  • Version1
    小波包分解,重构轴承振动信号,Hilbert包络,FFT进行频谱分析,以获得轴承故障频率。(Wavelet packet decomposition, reconstruction of bearing vibration signal, Hilbert envelope, FFT spectrum analysis to obtain the bearing fault frequencies.)
    2013-07-17 11:37:05下载
    积分:1
  • ddr2_controller
    A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.
    2015-11-16 00:31:22下载
    积分:1
  • 696516资源总数
  • 106914会员总数
  • 0今日下载