对于一个扫描程序的编写进行VHDL开发环境

This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)

VERILOG语言速查手册,与VHDL齐名的另外一硬件描述语言(verilog language manuals, and the other enjoying VHDL hardware description language 1)

说明：  关于quartus与modelsim 仿真(about quartus and modelsim simulator)

verilog code for bus controller

在fpga中对GPS信息采集程序。具有很好的参考性(In the fpga in the GPS information collection procedures. Has a very good reference)

蜂鸣器音乐演奏，有ppt说明，及实例工程文件。(Music buzzer, a ppt notes, and examples of engineering documents.)

基于fpga的数字电压表的设计，包括ad转换，bcd码转换，分频，3选1模块，小数点生成模块，显示模块组成。(Based on the FPGA digital voltage meter design, including AD conversion, BCD code conversion, frequency,3 choose1module, a decimal point generating module, display module. )

调制解调器是在发送端通过调制将数字信号转换成模拟信号，而在接收端通过解调将模拟信号转换为数字信号的一种装置。这个程序用VHDL语言编写，实现了二进制振幅键控（2ASK）的调制与解调；二进制频移键控（2FSK）的调制与解调，二进制相位键控（2PSK）的调制与解调过程。

采用Quartus2编写的电子秒表电路 实现计时、暂停等功能(Quartus2 prepared using electronic stopwatch timer circuit, suspension and other functions)

本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。-This procedure for 24-hour timer, stable error-free. Easy-to-use, is the Verilog HDL language beginners guide.