对于一个扫描程序的编写进行VHDL开发环境

altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中-ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II

verilog motor control

验证阻塞赋值与非阻塞的赋值赋值过程的先后顺序(Verification of the order of assignment and non blocking assignment)

verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)

针对某船舶模型定位系统中调速电机，以FPGA(现场可编程门阵列)为控制器，采用数字比例积分调节器实现电机的速度控制算法，设计出数字化调速控制器(Positioning system for a ship model in the motor speed, the FPGA (field programmable gate array) for the controllers, proportional integral regulator with digital speed of the motor control algorithm, designed digital speed controller)

小波提升算法源码，里面一个txt文件可以当作算法参考；(Wavelet lifting algorithm source code, inside a TXT file can be used as algorithm reference;)

xilinx公司的virtex-5开发板原理图 需要的可以下载看一下 希望对你有帮助(xilinx company virtex-5 development board schematics can download look you want to help)

可测试74LS00，74LS01，74LS02，74LS03等等芯片的功能是否正常。

实现一个循环冗余码,是老师给的例子，别的同学已经验证-a cycle ruduandency code

Variable Reduction Testbench通过对变量进行相关性分析来实现减少变量的目的。-Variable Reduction Testbench is a MATLAB module that allows the application of several methods for variable reduction based on correlation analysis