通过vhdl实现ls138硬件功能 通过vhdl实现ls138硬件功能

// -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined-//-*- Mode: Verilog-*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISH

说明：  FPGA串口实现。 发送和接受数据功能代码(FPGA serial interface. Send and receive data function code)

该书介绍了英特尔的80x86CPU和一些串行通信芯片，以及汇编语言。(The book introduces the Intel 80x86CPU and some serial communications chip, and assembly language.)

LTE is an abbreviation for Long Term Evolution.

ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.-Altera FPGA IP core of the source code for the use of Altera FPGA design to provide the relevant information.

设计制作一个检测4*4矩阵键盘的按键编码的实验，把实际按键的键值的八位编码先转换成从0000—1111的编码，再译成数码管能识别的八位编码，在数码管动态显示时，4*4矩阵键盘的第一行对应00—03，第二行对应04—07，第三行08—11，第四行对应12—15。(Design a 4* 4 matrix keyboard key coding experiments to detect the key the actual key octet coded first convert from 0000-1111 encoding, and then translated into digital tube to identify the eight coding, digital tube dynamic display, the first line of the 4* 4 matrix keyboard corresponding to 00-03, the second line corresponds to 04-07, the third line of 08-11, the fourth line corresponds to 12-15.)

用VHDL语言实现数字钟的设计，要求设计实现一个具有带预置数的数字钟，具有显示年月日时分秒的功能。用6个数码管显示时分秒，set按钮产生第一个脉冲时，显示切换年月日，第2个脉冲到来时可预置年份，第3个脉冲到来时可预置月份，依次第4、5、6、7个脉冲到来时分别可预置日期、时、分、秒，第 8个脉冲到来后预置结束，正常工作，显示的是时分秒。Up为高电平时，upclk有脉冲到达时，预置位加1.否则减1。

Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考.-Clock_Dithering_Verilog this is a Clock u_dither, everybody want to make Verilog-jitter can refer to.

用vhdl描写的通用异步改进dram控制器，经过编译器综合和仿真测试，符合设计要求。-Using VHDL description Universal Asynchronous improved dram controller, through an integrated compiler and simulation testing, in line with the design requirements.

说明：  altera 最新的CYCLONE IV的pci-e核的testbench，VHDL源程序。(altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.)