de2_clock on altera de2 board

5分代码及说明，verilog代码，几乎所有的IC面试都会问到这个问题，所以总结了一下发了上来，共同学习！-5 pm code and explanations verilog code Almost all the interviews will IC asked this question, summed up in the ranks about fat, learn together!

CY7C63723 功能及其引脚描述，外围电路和仿真数据(The CY7C637 is an 8-bit RISC OTP microcontroller.)

AGC(自动增益放大) Verilog代码 设计可以参考 第二部分(AGC (automatic gain control) can refer to the Verilog code design )

cordic 算法知道正弦和余弦值，求反正切，即角度。(The CORDIC algorithm knows sine and cosine values and asks for inverse tangent, that is, angle.)

多功能数字时钟 功能齐全 vhdl fp-Multi-functional digital clock vhdl fpaa

FPGA设计的四种常用思想与技巧，包括乒乓操作、串并转换、流水线操作、数据接口同步化(FPGA design of the four common ideas and techniques, including the operation of ping-pong, SERDES, pipelining, synchronization of data interface)

按键在数字电路设计中经常用到。按键的弹跳现象是数字系统设计中存在的客观问题。按键是机械触点，当接触点断开或闭合时会产生抖动。为使每一次按键只做一次响应，就必须去除抖动。本文对按键的抖动信号进行了分析，并通过计数器的方式完成了消除抖动电路模块的设计-?

说明：  功能是（用Verilog语言的，内有比较详细的注释）： （1）计数器的功能是从0到9999计数，并能以十进制数的形式在七段数码管上显示出来(包括七段数码管显示模块). （2）该计数器有一个1个nclr和一个adj_plus端，在控制信号的作用下（见下表），计数器具有复位、增或减计数、暂停的功能。编写以上的程序的完整模块. 计数器的功能表 nclr adj_minus 功 能 0 0 复位为0 0 1 递增计数 1 0 递减计数 1 1 暂停计数 (Function is (with Verilog language, the more detailed comments): (1) counter function is from 0 to 9999 counts, and are able to form a decimal number on the seven-segment LED display (including the seven-segment LED display module). (2) The counter has a one nclr and a adj_plus side, under the action of the control signal (see below), the counter has reset, increase or decrease of count pause function. Complete the preparation of the above program modules. Counter function menu nclr adj_minus reset 0 0 0 0 1 1 0 counts counting suspended Count 1 1)

在SOPC下制作自定义部件（PWM发生器）的源程序，包括硬件描述HDL文件和驱动程序文件-Produced in the SOPC custom component (PWM generator) of the source, including hardware description HDL files and driver files

利用AT89C51实现LCD日历电子钟源码-AT89C51 realization of the use of electronic LCD calendar clock source