xc2s100E FPGA的原理图 给想涉足FPGA的新人参考

r80515源代码，包含说明文档。FPGA验证通过(r80515 source code, including documentation. Verified by FPGA)

用于实现两个数相加的vhdl代码，在相应的编译器中使用-used to achieve the two summed VHDL code, the corresponding use of compiler

此代码完成了流水线CPU的设计。其中有ALU，控制模块，UART等verilog代码。(This code completes the design of pipelined CPU)

Turbo码编解码的FPGA实现，verilog语言编写(Implementation ofTurbo code on FPGA , using Verilog language)

是codic算法实现atan的C程序，包括定点和浮点程序，已经通过验证。(Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated.)

Verilog实现高速AD7606数据采样，8通道，采样频率可调，支持串口数据发送，亲测可用。(Verilog AD7606 high-speed data sampling, 8-channel, the sampling frequency is adjustable, support for serial data transmission, pro-test is available.)

这是一个讲究的的 介绍VB在犀牛软件里的 很好的东西 你会满意的 相信我(you will be glad)

用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。(Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.)

Nexys-4-DDR-XADC 开发板demo(Nexys-4-DDR-XADC e.v. Board demo)

Alter kit FPGA de2-35 This project shows a cascade motion through board leds.-Alter kit FPGA de2-35 This project shows a cascade motion through board leds.