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Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
- 2022-07-06 17:29:44下载
- 积分:1
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Verilog_135example
关于硬件描述语言Verilog的135个经典实例,从易到难,对Verilog的编程有很大的帮助。(About the Verilog hardware description language 135 classic example, from easy to difficult, for Verilog programming of great help.)
- 2013-06-17 10:29:43下载
- 积分:1
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sgiarcs
ARC firmware interface defines.
- 2015-06-27 18:50:37下载
- 积分:1
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ISE
设计一4位比较器,画出门级电路图,用verilog语言完成设计。
(Design a four comparators, drawing out level circuit diagram, complete the design using verilog language. )
- 2015-12-11 21:16:12下载
- 积分:1
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E1(一级欧洲传输标准)的VHDL
E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)vhdl
- 2022-04-22 01:03:35下载
- 积分:1
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Quartus II
quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE
- 2022-08-09 10:55:42下载
- 积分:1
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8 位加法器
有一个 8 位全加器 VHDL 代码。我测试该代码在协同,看到了这段代码的工作。
- 2022-04-21 11:16:03下载
- 积分:1
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FPGA design of the guiding principles, it is classic! Want to give everyone easy
FPGA设计的指导原则,很经典的!希望给大家方便-FPGA design of the guiding principles, it is classic! Want to give everyone easy
- 2023-03-11 18:40:04下载
- 积分:1
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update-for-the-item-CVFX-C02
This is the update firmware for CVFX-C02, 7" motorized touch screen car dvd player gps
- 2013-06-30 03:39:08下载
- 积分:1
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sdr_sdram
文章详细讲述了sdr_sdram控制器的使用和编程思想(sdr_sdram)
- 2009-06-11 01:48:25下载
- 积分:1