Using VHDL realize CPLD (EMP240T100C5) of the PWM output

很好的tft参考实列，通用的8位并口，非常快移值-Tft good reference is listed, eight general-purpose parallel port, very fast shift value

在quartus平台下使用verilog语言编程实现简单的单流水线CPU，可以执行16条基本指令(Quartus platform in the verilog language programming using a simple single-line CPU, can perform 16 basic instructions)

用verilog写的简单的CPU，有详细注释(Use verilog to write a simple CPU, with detailed notes)

2008-2009年优秀硕士论文之：基于FPGA的高性能32位浮点FFT IP核的开发(Outstanding Master' s thesis 2008-2009: FPGA-based high-performance 32-bit floating-point FFT IP core development)

I2C总线控制器 altera提供的VHDL的源程序代码-I2C Bus Controller ALTERA the VHDL source code

实现一个循环冗余码,是老师给的例子，别的同学已经验证-a cycle ruduandency code

QPSK调制下的（5,7）卷积码的编码和维特比译码与BPSK调制下（5,7）卷积码的编码和维特比译码的BER特性(QPSK modulation under (5,7) convolutional code encoding and Viterbi decoding and BPSK modulation (5,7) convolutional code encoding and Viterbi BER characteristic)

用VHDL编写的串口通讯程序，包括几个不同的程序例子，也可以用verilog进行改写。()

采用xilinx三太以太网ip核，tri-mode MAC完成千兆以太网数据传输(Too Ethernet using xilinx ip three nuclear, tri-mode MAC Gigabit Ethernet data transmission is completed)

说明：  URISC的RTL级设计，Verilog代码(Design: URISC RTL Verilog)