256字节深度的RS232串口程序,共分4个模块,顶层文件FIFO程序串口收和串口发.经过测试已用于产品.可靠!...

在开发板EGO1上实现的图形记忆游戏，白块按下确认建，黑色块不按确认键(memory game in verilog)

常用的VHDL语言编写的LED灯控制程序,这是教学用的，开发板采用的是EPM240T100C5N，买开发板时附带的程序

是一个LED点阵显示屏的原理图，非常详细，适合开发者学习(LED dot matrix display is a schematic diagram is very detailed, for developers to learn)

低通滤波器（由matlab和simulink两种方法实现）源文件及图片示例(Low-pass filter) source file and photo examples (by the two methods matlab and simulink)

RS 编码和解码Verilog Code, 实现了RS（204,188)的编码和译码；(RS Coding and Decoding Verilog code，　implement RS（204,188) )

this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for ps/2 interface .-this is a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for ps/2 interface .

说明：  rgmii代码编写，实现rgmii接口功能，可进行参考设计(The rgmii code is written to realize the function of rgmii interface, which can be used for reference design)

说明：  Vivado是Xilinx最新的FPGA设计工具，支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比，Vivado可以说是全新设计的。无论从界面、设置、算法，还是从对使用者思路的要求，都是全新的。看在Vivado上，Tcl已经成为唯一支持的脚本，此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)

特权同学主讲的FPGA设计的时序约束专题（STA部分）(Speaker privileged classmates timing constraints for FPGA design topics (STA section))

这是一个用vHDL语言实现的移位器，可以实现移位功能-This is the design of an shifter using vhdl